Taiwan Semiconductor Manufacturing Comp. Ltd.

Nuvoton Technology Corporation

Food Industry Research and Development Institute

I-Ching Chen

Wen-Ting Chu

Yu-Wen Liao

Chih-Yang Chang

Hsia-Wei Chen

Chin-Chieh Yang

Sheng-Hung Shih

Jen-Sheng Yang

Tung-Sheng Hsiao

Wei Cheng Wu

Kuo-Chi Tu

Gwo-Fang Yuan

Ing-Er Hwang

Li-Ling Liaw

Chien-Hsun Huang

Li-Wen Hsu

Yi-Ju Liu

Sung-Yuan Hsieh

Chien-Chi Chen

Jong-Shian Liou

En-Hui Kuo

The present disclosure provides a power control method for a microcontroller unit (MCU) and a power control system using the same. The power control method includes after a triggering event of switching CPU frequency occurs, controlling, through a power controller, a low dropout linear regulator (LDO) to output a preset voltage and triggering a clock controller to switch a first central processing unit (CPU) frequency; after the clock controller switches the first CPU frequency, counting, through a clock counter, a number of times of occurrence of a CPU clock within a period to obtain a second CPU frequency; and determining, through the power controller, a corresponding voltage of the second CPU frequency and controlling the LDO to output the corresponding voltage.

Power control method for microcontroller unit and power control system using the same

A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Microcontroller and memory control method thereof

Disclosed herein is an isolated strain ofHGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain ofHGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

HGM001 isolate and use thereof

Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Flat bottom electrode via (BEVA) top surface for memory

Method for forming a flat bottom electrode via (BEVA) top surface for memory

A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.

Step height reduction of memory element

An integrated circuit (IC) using high-&#x3ba; metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high &#x3ba; dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-&#x3ba;-last method for manufacturing the IC is also provided.

High-K-last manufacturing process for embedded memory with silicon-oxide-nitride-oxide-silicon (SONOS) memory cells

An integrated circuit (IC) using high-&#x3ba; metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high &#x3ba; dielectric layers. A high-&#x3ba;-last method for manufacturing the IC is also provided.

High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells

Promoters and usage thereof. Two promoters, acuF and hsp promoters, comprise the nucleotide sequences of SEQ ID NO: 1 and 2, respectively.

Promoters and usage thereof

Growing community of inventors

Hsinchu, Taiwan

I-Ching Chen