Advanced Micro Devices Corporation

I-Cheng K Chen

Francis M Matus

Kevin John McGrath

Ramsey W Haddad

Bruce R Holloway

A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.

Selective zero extension based on operand size

An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted. In one embodiment, the indirect branch predictor may include a second buffer indexed by a portion of the PC of the particular indirect branch instruction being predicted. The second buffer may store target addresses corresponding to previously executed indirect branch instructions and prediction selection information which may be used to select a target address prediction from one of the buffer and the second buffer. The second buffer may accurately predict indirect branch instructions whose target addresses are relatively fixed, using the buffer indexed by history information to predict the indirect branch instructions having more frequently changing indirect targets.

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Sunnyvale, CA, United States of America

I-Cheng K Chen