Realtek Semiconductor Inc.

Mediatek Corporation

Ralink Technology Corporation

Integrated Device Technology, Inc.

Mediatek Singapore Pte. Ltd.

I-Chang Wu

Keng Leong Fong

Chia-Liang (Leon) Lin

Fei Song

Chungwen Dennis Lo

Alireza Shirvani-Mahdavi

Jagdeep Singh Bal

Osama K A Shana'a

Chiyuan Lu

YuenHui Chee

Chihtung Chen

Yi-Te Yeh

Huai-Yu Yen

Hsing-ting Yu

Chia-Hsien Cheng

Chung Wen Lo

A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.

Temperature compensated voltage-controlled oscillator

A device includes a coil configured in a loop topology starting from a first end and extending to a second end, a pair of inward extension legs configured to extend from the first end and the second end toward an interior side of the coil to a third end and a fourth end, respectively, a pair of outward extension legs configured to extend from the first end and the second end toward an exterior side of the coil to a fifth end and a sixth end, respectively, a first capacitor configured to provide a capacitive coupling between the first end and the second end, a second capacitor configured to provide a capacitive coupling between the third end and the fourth end, and a third capacitor configured to provide a capacitive coupling between the fifth end and the sixth end.

LC tank circuit having improved resonant frequency stability and fabrication method thereof

A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

High-Q integrated inductor and method thereof

A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

Testing method and testing system

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

Wideband adaptive bias circuits for power amplifiers

Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage. In operation, an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog signal.

Methods and systems for analog-to-digital conversion (ADC) using an ultra small capacitor array with full range and sub-range modes

A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

Signal duty cycle detector and calibration system

A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.

Method using digital phase-locked loop circuit including a phase delay quantizer

A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.

Digital phase-locked loop circuit including a phase delay quantizer and method of use

Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.

Fast-response phase-locked loop charge-pump driven by low voltage input

Phase-locked loop charge pump driven by low voltage input. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current transistor providing a sourcing current, wherein the sourcing current transistor is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump, and a sinking control circuit uses low-voltage sinking control signals to selectively cause the charge pump to sink the sinking current from the output.

Fast response phase-locked loop charge-pump driven by low voltage input

One embodiment of the present invention includes a frequency generation circuit including a control module, an oscillator circuit coupled to the control module, the oscillator circuit having a start-up time defined by the time required to reach a desired frequency. The oscillator circuit includes an amplifier having an input and an output and being programmably-alterable by the control module, a first capacitor coupled to the input of the amplifier and being programmably-alterable, in capacitance, by the control module, a second capacitor coupled to the output of the amplifier, a crystal resonator coupled to the first and second capacitors for generating an output signal having a desired frequency, wherein fast start-up time is achieved.

Growing community of inventors

Fremont, CA, United States of America

I-Chang Wu