United Microelectronics Corp.

Calcitec, Inc.

Cana Lab Corporation

Other

I-Chang Wang

Chien-Ping Ju

Jiin-Huey Chern Lin

Kuan-Liang Lin

Ling-Chun Chou

Wen-Cheng Chen

Ching-Wen Hung

Chieh-Te Chen

Shin-Chi Chen

Shin-Chuan Huang

Guang-Yaw Hwang

Wei-Chih Chen

Teng-Chuan Hu

Yi Chuen Eng

Hsiu-Kuan Hsu

Chin-Cheng Chien

Jiunn-Hsiung Liao

Chiu-Hsien Yeh

Ming-Tsung Chen

Pau-Chung Lin

Yu-Hsiang Hung

Po-Chao Tsao

Chih-Sen Huang

Chih-Hung Tsai

Hui-Ling Chen

Hsiang-Ying Wang

Tsung-Hung Chang

Cheng-Yen Wu

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

Planar field effect transistor

Semiconductor process

Semiconductor process, planar field effect transistor and fin-shaped field effect transistor

A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.

Gate structure and method for trimming spacers

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Strained silicon structure

A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Spacer scheme for semiconductor device

A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Semiconductor device and manufacturing method thereof

A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.

Method for forming semiconductor device

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Method for fabricating semiconductor device

A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.

Method of fabricating n-channel metal-oxide semiconductor transistor

A method for increasing working time/setting time of monolithic tetracalcium phosphate (TTCP) cement paste formed by mixing a TTCP powder with an aqueous solution, which includes heating the TTCP powder, prior to the mixing, so that the TTCP powder is maintained at a temperature of 50-350&#xb0; C. for a period of time which is greater than one minute, and that a TTCP cement paste formed by mixing the resulting heated TTCP powder with the aqueous solution has a prolonged working time in comparison with that formed by mixing TTCP powder that has not been subjected to such heating with the aqueous solution.

Method of increasing working time of tetracalcium phosphate cement paste

A fast-setting, bioresorbable calcium phosphate cement is prepared by a process which can be carried out with a heat treatment up to 1000&#xb0; C. on a mixture of a wetting solution and a calcium phosphate powder having a Ca to P molar ratio of 0.5-2.5. The wetting solution suitable for use in the process of the present invention includes water, an organic solvent, an acidic and basic solution. A setting solution for mixing with the heated powder to form the fast-setting, bioresorbable calcium phosphate cement may be water, an acidic or basic solution according to the process of the present invention.

Process for affecting the setting and working time of bioresorbable calcium phosphate cements

A fast-setting, bioresorbable calcium phosphate cement is prepared by a process which can be carried out with a heat treatment up to 1000&#xb0; C. on a mixture of a wetting solution and a calcium phosphate powder having a Ca to P molar ratio of 0.5&#x2013;2.5. The wetting solution suitable for use in the process of the present invention includes water, an organic solvent, an acidic and basic solution. A setting solution for mixing with the heated powder to form the fast-setting, bioresorbable calcium phosphate cement may be water, an acidic or basic solution according to the process of the present invention.

Process for affecting the setting and working time of, bioresorbable calcium phosphate cements

A tetracalcium phosphate (TTCP) particle for use in preparing a fast-setting, bioresorbable calcium phosphate cement is disclosed. The TTCP particle has a basic calcium phosphate whiskers on a surface thereof; the basic calcium phosphate whiskers having a Ca/P molar ratio greater than 1.33, and having a length up to about 5000 nm and a width up to about 500 nm. The basic calcium phosphate whiskers are substantially free of a hydroxyapatite phase and mainly composed of TTCP phase.

Growing community of inventors

Tainan, Taiwan

I-Chang Wang