Samsung Electronics Co., Ltd.

Yonsei University

Skhynix Inc.

Hyunwuk Lee

Won Woo Ro

Gun Ko

Ipoom Jeong

Jiwon Lee

Jonghyun Lee

Min Seong Kim

Sung Jae Lee

Hongju Kal

Yong Tag Song

Seunghyun Jin

A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.

Memory management unit and method of walking page table

An apparatus and method with register sharing are provided. In one general aspect, a method of operating a processing apparatus includes determining whether there is shared data that is used by each of threads in a plurality of threads sharing a shared memory, based on an instruction that has been decoded, based on determining whether there is shared data that is used by each of the threads in the plurality of threads, determining whether an address of the shared data corresponding to each of the threads in the plurality of threads is stored in an address-to-register mapping table, based on a result of either the determining whether the address is stored in the address-to-register mapping table, mapping the address of the shared data to a shared register corresponding to the shared data, and loading the shared data based on the shared register.

Apparatus and method with register sharing

A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.

Memory device including a plurality of area having different refresh periods, memory controller controlling the same and memory system including the same

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Seoul, South Korea

Hyunwuk Lee