Samsung Electronics Co., Ltd.

Hyunwook Lim

Woohyuk Jang

Kyungho Ryu

Kilhoon Lee

Jinyong Park

Jaeyoul Lee

Hongki Kwon

Hyeonsu Park

Unki Park

Hojun Chung

TaeWoo Kim

Yong-Yun Park

Kyongho Kim

Youngmin Choi

Yonghoon Yu

Yongil Kwon

Jung-Pil Lim

Minsik Kim

Se Whan Na

Jiheon Ok

Byeongcheol Jang

Jungpil Lim

Jonghee Na

Jinho Kim

Sunkwon Kim

Bumsoo Kim

Yoon-Kyung Choi

Junchul Park

Eun-young Jin

Byoungyoon Jang

Taekon Yu

Jonghyuk Lee

Taeho Lee

Wongab Jung

Kyungae Kim

Jaehun Kim

Byunghwee Park

Gwangho Nam

Sewhan Na

Jooyoung An

Yeongcheol Rhee

Alankyongho Kim

Younghwan Chang

Kwi Sung Yoo

Taewoo Kim

Heejin Lee

Dong-hoon Baek

Uijong Song

Sugyeung Kang

Yilho Lee

Jong-Hee Na

Wangsuk Sung

Kang Joo Kim

Sengsub Chun

Seng-Sub Chun

Hansu Pae

Youngseo Kim

Pilseung Heo

Yoochae Chung

Yongyun Park

Junil Park

Alan Kyongho Kim

Seong-young Ryu

Provided is a communication system including a first electronic device and a second electronic device connected with each other through first and second channels. The second electronic device includes a reception driver generating a first internal signal based on a first data signal provided by the first electronic device through the first channel, an error detector generating an error detection signal by determining whether an error is included in the first internal signal, and an error adjuster outputting a first feedback signal through the second channel based on the error detection signal, and the first electronic device outputs a second data signal having a voltage swing width determined based on the first feedback signal through the first channel.

Electronic device and communication system including the same

The present disclosure provides transmitter circuits and display devices including the same. In some embodiments, the transmitter circuit includes a run length detector, a modifier, and a scrambler. The run length detector is configured to derive position information indicating a first input data related to a threshold run length from among a plurality of input data in a predetermined bit unit, when a run length of first scrambled data for the first input data meets or exceeds the threshold run length in the predetermined bit unit. The modifier is configured to generate modified input data by inverting at least one bit of the first input data based on the position information. The scrambler is configured to receive the modified input data from the modifier, and generate second scrambled data by scrambling the modified input data with scrambling information.

Transmitter circuit and display device including the same

To compensate for degeneration of an electroluminescent display device, a method of compensating for the degeneration may include, grouping a plurality of pixels in a display panel into a plurality of pixel blocks arranged in present block rows and present block columns based on initial block boundaries, accumulating block stress values based on input image data, each accumulated block stress value representing a degeneration degree of the pixels included in each pixel block of the plurality of pixel blocks, performing a boundary updating operation on the plurality of pixel blocks, the performing the boundary updating operation including moving present block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values, and correcting the input image data based on the accumulated block stress values and the updated block boundaries.

Method of compensating for degeneration of electroluminescent display device and display system performing the same

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Clock and data recovery circuit and a display apparatus having the same

A display driver circuit receives externally-encoded image data and processes the data using a memory (graphic RAM), an internal encoder, and an external decoder configured to operate on the externally-encoded image data. The processed data is provided to a display device by a source driver of the display driver circuit. Data is processed through the graphic RAM and an internal decoder or the external decoder depending on whether a slice of the data is a currently received update slice, a recently received standby slice, or a still slice.

Display driving circuit and operating method for performing encoding and decoding

A display device is provided. The display device includes: a pixel array including pixels connected to gate lines and source lines; and a driving circuit configured to: apply gate signals to the gate lines and provide data signals to the source lines during a first scan period such that horizontal periods of the gate signals do not overlap each other, and apply the gate signals to first gate lines, of the gate lines, connected to pixels in a first area of the pixel array in a different manner from second gate lines, of the gate lines, connected to pixels in a second area of the pixel array for a portion of a second scan period, provide the data signals to the source lines, and maintain a low-biased state or an off state for a remaining portion of the second scan period.

Display device and driving method thereof

Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes 'M' consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

Electronic device and operating method of a decoder

In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.

Backlight apparatus and operating method thereof

The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.

Semiconductor device and operating method thereof

A display driver integrated circuit includes a frame buffer, a plurality of image processing circuits and an image processing controller. The frame buffer sequentially stores a plurality of frame data received from a host processor. Each of the plurality of frame data includes a plurality of data slices. The image processing circuits perform image signal processing operations, respectively, on ones of the data slices that are included in a respective one of the plurality of frame data and which are sequentially retrieved from the frame buffer. The image processing controller bypasses at least one of the image processing circuits by applying a bypass control signal to the image processing circuits based on a first plurality of data slices included in a first one of the plurality of frame data and a second plurality of data slices included in a second one of the plurality of frame data.

Display driver integrated circuit and method of operating the same

A touch sensor controller for driving a touch sensor that is stacked on a display panel and includes driving electrodes and receiving electrodes crossing the driving electrodes, the touch sensor controller including: a driving circuit configured to sequentially provide driving signals to the driving electrodes; a read-out circuit configured to, in response to the driving signals, generate touch data based on first sensing signals received from the receiving electrodes and generate display noise data based on a second sensing signal received from a first driving electrode to which a driving signal of the driving signals is not applied from among the driving electrodes; and a touch processor configured to determine whether a touch input has occurred on the touch sensor based on the touch data and the display noise data.

Touch sensor controller, operating method of touch sensor controller, and touch screen driving circuit

Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.

Display driving circuit, display device including the same, and method of operating the same

An electronic device includes a display panel that includes a first region including first pixel groups and a second region including second pixel groups, and a compensation circuit. The compensation circuit may receive first image data. The compensation circuit may compensate to generate second image data in response to a determination that the first image data corresponds to at least one of one or more particular first pixel groups that are adjacent to a boundary between the first region and the second region or one or more particular second pixel groups that are adjacent to the boundary. The compensation circuit outputs the second image data to the display panel.

Electronic devices and operating methods of electronic devices

A display device includes a display panel including an under display camera (UDC) region and a non-UDC region, the UDC region including a plurality of sub-regions, and processing circuitry configured to, receive image data, select at least one first filter from a plurality of filters based on a spatial coordinate value of the received image data, the plurality of filters corresponding to a respective sub-region of the plurality of sub-regions, and perform first pixel rendering for the UDC region based on the at least one first filter and the image data, and the at least one first filter is generated based on a pixel arrangement pattern of the UDC region.

Display device and operating method of display device

Provided are a low-power display driving circuit performing internal encoding and decoding and an operating method thereof. The display driving circuit includes a memory configured to store an input bit stream encoded by an encoder and a controller configured to determine a data path through which output frame data in a second frame period passes according to whether internal encoding is successful in a first frame period, wherein, when the internal encoding is successful, the controller performs internal encoding in the second frame period, stores a generated internal bit stream in the memory, allows the internal bit stream to pass through a low-power path to generate the output frame data, and when the internal encoding fails, the controller generates the output frame data by allowing the input bit stream to pass through a normal path in the second frame period, changes an encoding setting of an internal encoder, and repeats the internal encoding.

Low-power display driving circuit performing internal encoding and decoding and operating method thereof

Growing community of inventors

Seoul, South Korea

Hyunwook Lim