Globalfoundries Singapore Pte. Ltd.

Everspin Technologies, Inc.

Hyunwoo Yang

Juan Boon Tan

Alex See

Wanbing Yi

Danny Pak-Chum Shum

Curtis Chun-I Hsieh

Soh Yun Siah

Hai Cong

Naganivetha Thiyagarajah

Young Seon You

Jon Michael Slaughter

Sarin A Deshpande

Suk Hee Jang

Shukai Ye

De Wei Shawn Wong

Cong Hai

A semiconductor device may be provided, including a first dielectric layer having a first region and a second region laterally adjacent to the first region. The semiconductor device may further include a bottom electrode at least partially arranged within the first region of the first dielectric layer, a memory element arranged over the bottom electrode, a top electrode arranged over the memory element, and a second dielectric layer arranged over at least the first region of the first dielectric layer. The second dielectric layer may surround the memory element and may surround at least a part of the top electrode. The semiconductor device may further include a third dielectric layer arranged over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer, and a conductive interconnect arranged in the third dielectric layer and the second region of the first dielectric layer.

Semiconductor device and method of forming the same

A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.

Methods of manufacturing integrated circuits using isotropic and anisotropic etching processes

Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.

Integrated two-terminal device with logic device for embedded application

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

Growing community of inventors

Singapore, Singapore

Hyunwoo Yang