Qualcomm Incorporated

University of Michigan

Hyunwoo Park

Kwanyong Lim

Stanley Seungchul Song

Junjing Bao

Youn Sung Choi

Ming-Huei Lin

Haining S Yang

Xia Li

Kira Barton

Peijie Feng

Neil P Dasgupta

Youseok Suh

Orlando Trejo

Ellis Herman

Lauren Ransohoff

Mattison Rose

Andre Brooks

Tae H Cho

Chih-Sung Yang

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

Self-aligned source/drain contact structure and method of manufacturing the same

A spatial atomic layer deposition apparatus that includes a depositor head having an active surface configured to discharge a flow of a first precursor gas, a flow of a second precursor gas, and a flow of an inert gas that separates the flow of the first precursor gas and the flow of the second precursor gas, a substrate plate that opposes the depositor head and has a support surface for retaining a build substrate, a plurality of gap detection sensors producing an output signal indicative of a distance between the active surface of the depositor head and the support surface of the substrate plate, and a controller that communicates with the plurality of gap detection sensors. The gap detection sensors permit a spatial orientation of the active surface of the depositor head and the support surface of the substrate plate to be determined in real-time and monitored.

Mechatronic spatial atomic layer deposition system with closed-loop feedback control of parallelism and component alignment

Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

Selective contact on source and drain

An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

Integrated device comprising a CMOS structure comprising well-less transistors

Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.

Leakage current reduction in polysilicon-on-active-edge structures

Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.

Sensor for gate leakage detection

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San Diego, CA, United States of America

Hyunwoo Park