Apple Inc.

Qualcomm Incorporated

Hyunwoo Nho

Jie Won Ryu

Hung Sheng Lin

Kingsuk Brahma

Junhua Tan

Sun-il Chang

Shengkui Gao

Hyunsoo Kim

Wei Hsin Yao

Jesse Aaron Richmond

Injae Hwang

Chaohao Wang

Shiping Shen

Myungjoon Choi

Rui Zhang

Chin-Wei Lin

Yafei Bi

Mohammad Bagher Vahid Far

Myung-Je Cho

Alex H Pai

Weijun Yao

Mohammad Ali Jangda

Yun Yu Wang

Paolo Sacchetto

Derek Keith Shaeffer

Shinya Ono

Majid Gharghi

Hopil Bae

Yingxuan Li

Marc Joseph DeVincentis

Xiaofeng Wang

Mohammad Hajirostam

Ahmad Al-Dahle

Marc Albrecht

Sang Young Youn

Baris Cagdaser

Haifeng Li

Yunhui Hou

Vehbi Calayir

Peter F Holland

Warren S Rieutort-Louis

Mahesh B Chappalli

Christopher P Tann

Wei Xiong

ByoungSuk Kim

Arthur L Spence

Koorosh Aflatooni

Yifan Zhang

Kwang Soon Park

Sean C Chang

Jiayi Jin

Yingying Tang

Howard H Tang

Yue Jack Chu

Rungrot Kitsomboonloha

Shatam Agarwal

Graeme M Williams

Pei-En Chang

Fan Gui

Wei Chen

Tsung-Ting Tsai

Marduke Yousefpor

Ting-Kuo Chang

Jim Chen Chou

Jean-Pierre Simon Guillou

Sei Seung Yoon

Seong-Ook Jung

Abbas Jamshidi Roudbari

Vasudha Gupta

Chieh-Wei Chen

Qing Li

Sheng Zhang

Jun Li

Prashant Mandlik

Nicolas P Bonnier

Szu-Hsien Lee

Kyung Wook Kim

Lu Zhang

Xiaokai Li

Zhen Zhang

Yi Qiao

Jiun-Jye Chang

Hao-Lin Chiu

Pierre-Yves Emelie

Guy Côté

Chun Lu

Xiang Lu

David S Zalatimo

Jenny Hu

Ching-Sang Chuang

Chengrui Le

Tobias Jung

Keitaro Yamashita

Peng Li

Taif Ahmed Syed

Jason N Gomez

Zino Lee

Luigi Panseri

Gihoon Choo

Yi-Pai Huang

To reduce overall power consumption for an electronic display power management integrated circuit (PMIC), one of multiple electric power converters and/or electric power regulators may be selected based on an electrical load (e.g., due to the total brightness of the content displayed) on the electronic display at a given moment. In some embodiments, the PMIC may include a less efficient heavy load converter designed with high-current handling capability and a more efficient light load (e.g., low current) converter with lower current handling capability. A controller may dynamically select between the converters depending on a present load or an expected load on the electronic display.

Content-aware dynamic power converter switching for power optimization

Electronic devices, displays, and methods are provided for performing pixel grouping to enable efficient display operation at higher frame rates and lower image resolutions without sacrificing significant image quality. An electronic display may include a number of rows of display pixels and driving circuitry. The driving circuitry may receive a frame of image data and drive a set of adjacent groups of rows of equal number using the frame of image data. Adjacent groups of rows may respectively include two or more adjacent rows.

Electronic display pixel grouping to mitigate motion blur

Embodiments herein provide various apparatuses and techniques to efficiently mitigate front-of-screen (FoS) artifacts that may occur due to voltage fluctuations due to alternating current (AC) or direct current (DC) mechanisms that may occur in a variety of pixel types. In one embodiment, emission profile awareness circuitry may be implemented to mitigate for FoS artifacts due to DC mechanisms. Two-dimensional (2D) digital compensation circuitry may address the DC portion of the voltage fluctuations by accounting for an emission profile applied to content displayed on an electronic display. In some embodiments, the 2D digital compensation circuitry may compensate for the AC portion of the voltage fluctuations by duplicating the AC voltage fluctuations via voltage error subtraction circuitry and voltage error accumulation circuitry.

Feedforward compensation of high-luminance banding Mura compensation

An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.

Display panel transistor gate-signal compensation systems and methods

An electronic display may include a touch sensing system configured to perform touch sensing in an active area of the electronic display and display driver circuitry configured to program display pixels of the active area to emit light. The electronic display may also include the active area. The active area may include a first portion and a second portion that are at least partially electrically separated. The display driver circuitry may program the display pixels in the first portion while the touch sensing circuitry may perform touch sensing in the second portion.

Split display driver circuitry to mitigate touch sensing system interaction

An electronic device may include processing circuitry configured to generate a first frame of image content and a second frame of image content. The second frame of image content is different from the first frame of image content. The electronic device may also include a display configured to display the first frame of image content at a first refresh rate. In response to receiving the second frame of image content, the electronic device may initially increase the refresh rate before tapering back to the first refresh rate while displaying the second frame of image content.

Frame insertion and frame rate sequencing for panel glitch prevention

An electronic device includes a display having multiple regions of pixels. Each pixel includes a diode that emits light based on an amount of current through the diode and a transistor that controls the amount of current flowing through the diode. The electronic device includes driver-integrated circuitry that reduces hysteresis in a first transistor of a first pixel of a region of pixels, settles a threshold voltage of the first transistor, applies a test voltage to the first transistor, and senses a current across the first transistor. The electronic device includes processing circuitry that determines a predetermined voltage based on the current and a predetermined current-voltage relationship determined at an initial temperature, determines a voltage difference between the test voltage and the predetermined voltage, and applies the predetermined voltage and the voltage difference to a second transistor of a second pixel of the region of pixels.

Systems and methods for external off-time pixel sensing

This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display.

Systems and methods for clock frequency control during low display refresh rates in electronic devices

This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.

Two-dimensional content-adaptive compensation to mitigate display voltage drop

An electronic device may include an electronic display having multiple display pixels to display an image based on analog voltage signals. The electronic device may also include optical calibration circuitry to generate digital-to-analog converter (DAC) data based on image data associated with the image and dither circuitry to reduce a bit-depth of the DAC data, generating dithered DAC data. Additionally, the electronic device may include a gamma generator having one or more DACs to generate the analog voltage signals based on the dithered DAC data, which may instruct the gamma generator to generate the analog voltage signals indicative of the image data.

Dither enhancement of display gamma DAC systems and methods

Systems, methods, and devices are provided for mitigating visual artifacts by dynamically tuning bias voltages applied to display pixels. An electronic display may include a display pixel and a bias voltage supply. The bias voltage supply may supply a first bias voltage to the display pixel for a first subframe of a frame of image data. The bias voltage supply may supply a different second bias voltage to the display pixel for a second subframe of the frame of image data. This may mitigate certain image artifacts, such as flicker or variable refresh rate luminance difference, that could arise due to display pixel hysteresis that varies across subframes of the image frame.

Dynamic voltage tuning to mitigate visual artifacts on an electronic display

External compensation of display panels may employ measurement or sensing circuitry configured to measure the output of a pixel and compensate for variations. Due to effects from the sensing circuitry, a mismatch between a target current and the actual current in the pixel may occur. Systems and methods that compensate for the effects from sensing circuitry and reduce or mitigate the mismatch are described. Systems and methods described herein include compensation circuitry that is capable of employing correction factors to compensate for the effects due to the presence of sensing circuitry. Methods for determining the correction factor are also described.

External compensation for displays using sensing and emission differences

Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

Mitigation of tearing from intra-frame pause

A current-voltage (IV) relationship of a pixel having a diode is initially determined. A first voltage is determined that does not cause the diode to emit light, and a first current across the diode is sensed by applying the first voltage. A predetermined current is determined based on the first voltage and the IV relationship. A ratio is determined based on the first current, a target current, and the predetermined current. A ratio voltage is determined by applying the ratio to a predetermined target voltage. If the first current is less than the predetermined current, then the ratio voltage is applied to supply a target current to the diode. If the first current is greater than the predetermined current, then a second voltage is determined by averaging the first test voltage and the ratio voltage, and the second voltage is applied to supply the target current to the diode.

Display compensation using current sensing across a diode without user detection

An electronic device may have a variable refresh rate display. Static content may be displayed on the display at a lower refresh rate than moving content to conserve power. The display may include an array of pixels. Display driver circuitry in the display may load image data into rows of the pixels. The display driver circuitry may have digital-to-analog converter circuitry that supplies data signals to the array. The display driver circuitry may respond to a variable refresh rate control signal that is asserted and deasserted depending on whether static or moving image content is to be displayed. The display driver circuitry may use the digital-to-analog converter circuitry to apply a time-varying scaling factor to the image data. The magnitude of the scaling factor may be adjusted during transitions between refresh rates to help suppress luminance variations that might otherwise result in flickering on the display.

Low-flicker variable refresh rate display

Growing community of inventors

Stanford, CA, United States of America

Hyunwoo Nho