Micron Technology Incorporated

Hyunui Lee

Yuan He

Takamasa Suzuki

Yasuo Satoh

Chiaki Dono

Won Joo Yun

Chikara Kondo

Baekkyu Choi

Masayoshi Yamazaki

The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Signal delay control and related apparatuses, systems, and methods

A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

Output impedance calibration, and related devices, systems, and methods

Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Reference-voltage-generators within integrated assemblies

Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Methods for improving timing in memory devices, and related devices and systems

A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Integrated assemblies having memory cells with capacitive units and reference-voltage-generators with resistive units

A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

Input/output capacitance measurement, and related methods, devices, and systems

Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.

Impedance calibration via a number of calibration circuits, and associated methods, devices, and systems

An output driver is disclosed. An output driver may include a pre-driver and a main driver coupled to the pre-driver. The main driver may include at least one switch, and a first transistor coupled between a first supply voltage and the at least one switch. The main driver may also include a second transistor coupled between a second, different supply voltage and the at least one switch. The at least one switch is configured to couple an output node of the output driver to one of the first transistor and the second transistor in response to receipt of a control signal. The main driver may also include a third transistor coupled between a reference voltage and the output node. An electronic system including at least one output driver, and methods of operating an output driver are also described.

Output drivers, and related methods, memory devices, and systems

Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.

Apparatuses and methods for providing clocks to data paths

Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

Growing community of inventors

Kanagawa, Japan

Hyunui Lee