Samsung Electronics Co., Ltd.

Hyuntaek Jung

Suk-Soo Pyo

Taejoong Song

Boyoung Seo

Gyuseong Kang

Artur Antonyan

Antonyan Artur

A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

Memory device including merged write driver

A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.

Nonvolatile memory devices having enhanced write drivers therein

A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.

Memory device for reducing leakage current

A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.

Nonvolatile memory device and operating method thereof

A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Nonvolatile memory device and operating method of nonvolatile memory device

An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.

A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing complementary data, thereby increasing or maximizing sensing margin. Also, the nonvolatile memory device connects a plurality of true cell/complementary cells to a word line, thereby markedly reducing the size of a memory cell array.

Growing community of inventors

Seoul, South Korea

Hyuntaek Jung