Samsung Electronics Co., Ltd.

Hyunsung Jung

Kyung Min Lee

Jung Hyuk Lee

Hyemin Shin

Yoonjong Song

Daeeun Jeong

Disclosed are memory devices including a variable resistance memory cell and a word line control circuit. A memory device including a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to the common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line, and a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation may be provided.

Memory device configured to perform asymmetric write operation according to write direction

Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

Memory device and programming method

A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

Memory devices configured to prevent read failure due to leakage current into bit line

A logic circuit may include at least one magnetic tunnel junction device including a first layer configured to receive a particular input signal and a second layer connected to a node, and an inverter connected to the node and configured to generate an output signal by inverting a signal of the node, wherein the inverter includes a transistor on a substrate, and the at least one magnetic tunnel junction device is on an upper portion of the transistor. The at least one magnetic tunnel junction device may include first and second magnetic tunnel junction devices configured to receive first and second input signals, respectively. The logic circuit may include a magnetic tunnel junction device and a reference resistor configured to receive a second input signal, the reference resistor connected to the node, the reference resistor having a reference resistance. The logic circuit may be included in an apparatus.

Logic circuits including magnetic tunnel junction devices

A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.

Growing community of inventors

Hwaseong-si, South Korea

Hyunsung Jung