Samsung Electronics Co., Ltd.

Hyunsun Ahn

Jaegon Lee

A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information.

System on chip including unified input/output memory management unit

A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.

Target device providing debugging function and test system comprising the same

A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.

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Seoul, South Korea

Hyunsun Ahn