The Boeing Company

Hyunsuk Shin

Sean M Ramey

Ronald James Koontz

Jason Ellis Sherrill

David Carl Matthews

Joshua R Byrne

Bruce A Boettjer

Dennis Kanarsky

Robert Horton

Forrest B Lee

Douglas M Mcintosh

The present application relates to systems, methods, and apparatus for synchronization of multiple processing devices. An exemplary system may include a memory device configured to store instructions and data for processing devices. A voting integrated circuit may be coupled to the memory device. The voting integrated circuit may be configured to receive output data from each of a plurality of processing devices and to perform voting between the output data to determine whether a plurality of output data is identical. The voting integrated circuit may be implemented using a field programmable gate array (FPGA).

Systems, methods and apparatus for synchronization of multiple processing devices

A system, method and computer program product to synchronize processing across multiple lanes. In a system, a synchronizing interface network controller (SINC) communicates with a plurality of processors. Each processor executes an application having thread(s) of operation. Each processor notifies the SINC when a specific thread is ready to perform a respective operation. The SINC releases the processors to perform the respective operation upon being notified by all processors that the specific thread is ready to perform the respective operation. Each processor is configured to monitor for the release of the processors and to also determine whether sufficient time remains within a time window to perform the respective operation. If insufficient time remains, a processor notifies the SINC that the specific thread is no longer ready to perform the respective operation. If the processors are released by the SINC while sufficient time remains, each processor performs the respective operation.

System and method for synchronizing processing between a plurality of processors

A method for synchronizing messages between processors is provided. The method comprising receiving, by a first external device, inbound messages for applications running redundantly in high integrity mode on two or more multi-core processors. The inbound messages are synchronously copied to the multi-core processors. The multi-core processors send outbound messages to respective alignment queues in the first external device or a second external device, wherein the outbound messages contain calculation results from the inbound messages. The first or second external device compares the alignment queues. Matched outbound messages in the alignment queues are sent to a network or data bus. Any unmatched outbound messages in the alignment queues are discarded.

Message synchronization system

Growing community of inventors

Los Angeles, CA, United States of America

Hyunsuk Shin