Samsung Electronics Co., Ltd.

Hyunseok Lim

Hyeonjin Shin

Kyung-Eun Byun

Jeonggil Lee

Yeonchoo Cho

Keunwook Shin

Shin-Jae Kang

Soyoung Lee

Jaejin Lee

Seunggeol Nam

Hyunjae Song

Sangho Rha

Hauk Han

Alum Jung

Seungjong Park

Kyung-Tae Jang

Kwangtae Hwang

Tai-Soo Lim

Jooyeon Ha

Kyoung Hee Nam

Seulgi Bae

Jungsoo Yoon

Sungjin Park

Sangwon Kim

Jinwoo Park

Dohyung Kim

Changseok Lee

Eunkyu Lee

Seok-Won Lee

Insun Park

Janghee Lee

Keun Young Lee

Gyuhwan Oh

Jiwoon Im

Jeonil Lee

Kihyun Yoon

Joyoung Park

Nak-Hyun Lim

Kaoru Yamamoto

Yu Seon Kang

Dong Hyeop Ha

Byungsun Park

Jiyoun Seo

Minhyuk Cho

Geuno Jeong

Taeyong Eom

Hyukho Kwon

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μmor higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Nanocrystalline graphene and method of forming nanocrystalline graphene

A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

Method of pre-treating substrate and method of directly forming graphene using the same

A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Wiring structures, methods of forming the same, and semiconductor devices including the same

A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

Method of forming nanocrystalline graphene, and device including nanocrystalline graphene

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same

A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

Semiconductor device and method of manufacturing the same

A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.

Semiconductor memory devices

Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

Three-dimensional semiconductor memory devices

Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Semiconductor device and method for forming the same

Semiconductor device and method of forming the same

Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

Variable resistance non-volatile memory cells and methods of fabricating same

Growing community of inventors

Suwon-si, South Korea

Hyunseok Lim