Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Samsung Sdi Co., Inc.

Corning Incorporated

Korea Advanced Institute of Science and Technology

Continental Automotive Gmbh

Hyunseok Kim

Soyeon Kim

Seoksoo Lee

Jusik Kim

Jinho Jang

Jaehyuk Kang

Michael Edward Badding

Zhen Song

Hoyeong Lim

Yongseung Yi

Dongil Son

Lincoln James Miara

Junghoon Park

Junho Huh

Seunggoo Kang

Doosuk Kang

Dongmin Im

Wonseok Chang

Gupil Cheong

Kihyun Park

Hongsoo Choi

SeWon Kim

Hyeokjo Gwon

Sungjun Choi

Saebom Ryu

Jae Min Kim

Hyunah Oh

Karen E Thomas-Alyea

Bumhee Lee

Hoil Jeon

Dongkyu Kim

Jungsik Park

Chul-Woo Lee

Sujin Lee

Gyu-Hyeong Cho

Seungbo Shim

Jaemin Kim

Jaehwan Lee

Sunghyup Lee

Ryounghee Kim

Kyungjin Lee

Jeonggyu Jo

Hyorang Kang

Heeseok Jung

Hyunseung Lee

Sungkyun Jung

Jenam Lee

Changhoon Jung

Byungchul Jeon

Seungsik Chun

Taehwan Yu

Gibeom Kim

Dongyup Lee

Euibum Han

Jesus Manuel Perez Pueyo

Hyun-Sik Yun

Shin-Ho Choi

Wooram Kim

Soohye Shin

Hyeongyu Cho

Sooyun Lee

Dayton Kim

Jison Im

Hoju Jung

Yongjun Yu

Joungwon Park

Sunwoo Kim

Jungseok Lee

Incheol Baek

Shintaro Kitajima

Beomju Kim

Jongkyu Lee

Hyeongsoon Park

Hyangbok Lee

Chang Seok Chae

Seungyun Lee

Moonki Yeo

Cheolyoon Chung

Siyoul Choi

Juseung Lee

Gyeong-Gu Kang

Junghyuk Kim

Daegun Kim

Younghoon Kwak

Gyucheol Han

Dahye Park

Heemun Bang

Se-Un Shin

Sungjin Moon

Sang-Hyen Park

Chiseon Won

Inhae Kang

Jaeyoul Oh

Jingyu Heo

Jeongjun Oh

Yongsoo Choi

Karen E Thomas-alyea

Yong-Gun Lee

Minyong Jung

Sewon Kim

A solid electrolyte including: a lithium ion inorganic conductive layer; and an amorphous phase on a surface of the lithium ion inorganic conductive layer, wherein the amorphous phase is an irradiation product of the lithium ion inorganic conductive layer. Also, the method of preparing the same, and a lithium battery including the solid electrolyte.

Solid electrolyte, method of preparing the same, and lithium battery including the solid electrolyte

There is provided an operation method of a memory system which includes a host and a storage device, and the operation method includes allocating a portion of a host memory included in the host for a host memory buffer to be used by a controller of the storage device, setting a set feature command such that the host memory buffer is enabled, setting a retention command including information about a response speed of the host memory buffer, selecting an operation mode of the host memory buffer, based on the retention command, and selecting one of a plurality of power states, which the controller supports, based on a performance objective of the operation mode of the host memory buffer.

Memory system using host memory buffer and operation method thereof

Disclosed is an electronic device including: a USB connector connected to a USB plug of an external device; a high-speed interface; a voltage source for supplying a voltage to the high-speed interface; a first circuit portion connected to a ground portion, and has a second impedance higher than a first impedance of the high-speed interface; and a processor. The processor is configured to monitor the external device by using the high-speed interface in a first interval of a first frame, form a disconnection sensing path by forming a connection between the first circuit portion and a second circuit portion of the external device, and use the disconnection sensing path to determine whether the connection between the USB connector and the USB plug has been disconnected. The second circuit portion may have a fourth impedance higher than a third impedance of an external high-speed interface. Various other embodiments are also possible.

Electronic device comprising connector and method for sensing disconnection

A compound represented by the Formula 1 and having an argyrodite-type crystal structure:LiM1M2PSM3  Formula 1wherein M1 is at least one element of Group 2 or Group 11 of the periodic table, M2 is at least one metal element other than Li of Group 1 of the periodic table, M3 is at least one element of Group 17 of the periodic table, and wherein 4≤a≤8, 0<x<0.5, 0≤w<0.5, 3≤y≤7, and 0≤z≤2.

Solid ion conductor, solid electrolyte including the solid ion conductor, electrochemical cell including the solid ion conductor, and preparation method of the same

A solid electrolyte includes a compound having an argyrodite crystal structure represented by Formula 1,LiMPSBrX.  Formula 1wherein Formula 1,

Solid electrolyte, electrochemical battery including the solid electrolyte, and method of preparing the solid electrolyte

A memory repair circuit of a memory module including a plurality of memory packages, the memory repair circuit including: a test circuit configured to test the plurality of memory packages to obtain fail information in each of the plurality of memory packages; and a redundancy analysis circuit configured to: obtain a redundant address count in each of the plurality of memory packages, determine a repair order of the plurality of memory packages based on the fail information and the redundant address count, and perform a virtual repair on the plurality of memory packages in the repair order to determine an address to be repaired in each of the plurality of memory packages.

Memory repair circuit, a memory repair method, and a memory device

A memory system includes a memory module and a memory controller to control semiconductor memory devices in the memory module. Each of the semiconductor memory devices provides the memory controller with an address of at least a defective memory cell row unrepairable with a redundancy resource in a memory cell array as unrepairable address information. The memory controller allocates a portion of a normal cell regions of at least one of the semiconductor memory devices as a reserved region, and remaps first and second unrepairable addresses to first and second physical addresses of the reserved region in response to first and second host physical addresses from a host matching the first and second unrepairable addresses, respectively. The first physical address and the second physical address are consecutive.

System and method for memory bad block mamagement

A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

System on chip and electronic device including the same

An electronic device comprises: a plurality of scalers for processing respective images of a plurality of content received from a plurality of sources devices; and a processor configured to change information on whether at least one scaler of the plurality of scalers supports high dynamic range (HDR) when a request for simultaneously displaying the plurality of content is received.

Electronic device and control method therefor

A compound represented by Formula 1 and having an argyrodite-type crystal structure:LiM1PSM2M3  Formula 1 In Formula 1, M1 is at least one metal element of Group 1 to Group 15 of the periodic table, except Li, M2 is SO, M3 is at least one element of Group 17 of the periodic table; and 4≤x≤8, 0≤v<1, 3≤y≤7, 0<w<2, 0≤z≤2, and 1.5≤n≤5.

Solid ion conductor compound, solid electrolyte including solid ion conductor compound, electrochemical cell including solid ion conductor compound, and method of preparing solid ion conductor compound

An operating method for a memory system including a host and a memory system. The operating method may include; communicating maximum power information from the memory system to the host, communicating power table information and battery information from the host to the memory system in response to the maximum power information, and controlling power consumption by a component of the memory system in response to a maximum consumption power value, wherein each of the power table information and the battery information is related to a battery associated with the memory system and operating in accordance with battery steps, the power table information includes a number of entries including a first entry and a second entry, the first entry is related to a first battery step among the battery steps and associated with a first maximum consumption power value, the second entry is related to a second battery step among the battery steps and associated with a second maximum consumption power value, and the maximum consumption power value controlling power consumption by the component of the memory system is one of the first maximum consumption power value and the second maximum consumption power value.

Memory controller adjusting power, memory system including same, and operating method for memory system

A solid electrolyte including an inorganic lithium ion conductive film and a porous layer on a surface of the inorganic lithium ion conductive film, wherein the porous layer includes a first porous layer and a second porous layer, and the second porous layer is disposed between the inorganic lithium ion conductive film and the first porous layer, and wherein the first porous layer has a size greater which is than a pore size of the second porous layer.

Solid electrolyte, method of preparing the same, and secondary battery including the same

A solid electrolyte including a compound represented by Formula 1:(LiM)PSNX  Formula 1wherein, in Formula 1,

Metal and nitrogen-including argyrodite solid electrolyte, electrochemical cell including solid electrolyte, and method of preparing solid electrolyte oxide

A positive electrode includes a composite material including a positive active material and a coating layer on a surface of the positive active material, wherein the coating layer includes a copolymer including a first repeating unit represented by Formula 1 below and a second repeating unit represented by Formula 2 below: wherein Ar, Rto R, A, A, Y, m, and n are the same as defined in the specification.

Positive electrode and lithium battery including the same

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Seoul, South Korea

Hyunseok Kim