Samsung Electronics Co., Ltd.

Hyunjun Yoon

Jinwoo Park

Heejin Kim

Yongsung Cho

Yoonhee Choi

Kitae Park

Jiyoon Park

Jaeyong Jeong

Dongkyo Shim

Ohsuk Kwon

Ju Seok Lee

Wontaeck Jung

Sungwon Yun

A memory device includes a memory cell array having memory cells therein that are programed to a plurality of program states, and a page buffer circuit having a plurality of page buffers therein that are connected to a plurality of bit lines associated with the memory cell array. Each of the page buffers includes a sensing latch that is connected to a corresponding one of the plurality of bit lines, and is configured to control a precharge operation performed on a corresponding bit line. Control logic is provided to control a verification operation performed on the plurality of program states within the memory cells by controlling the page buffer circuit, a plurality of dump operations on the sensing latch, which are based on values of at least two bits stored in each of the page buffers, and a selective precharge of bit lines that are connected to memory cells to be programmed to a first program state to be verified, from among the plurality of program states.

Memory device configured to reduce verification time and operating method thereof including dump operations

Provided are a non-volatile memory device, a storage device including the same, and a method of performing a programming operation on the same. The method includes performing a program operation including applying a desired first program voltage to a selected word line of the memory device, the selected word line including a plurality of memory cells, performing a verification operation including sensing a first sensing value corresponding to an output of the selected word line based on a first verify voltage, and counting a number of on-cells of the selected word line based on the first sensing value to determine a first count value, determining whether a first program state of the selected word line has been verified based on the first count value and at least one reference value, and setting a second program voltage based on results of the determining whether the first program state has been verified.

Storage device, non-volatile memory, and method of operating program of non-volatile memory including counting a number of on-cells during verification

A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

Page buffer circuit and memory device including the same

A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

Non-volatile memory device, method of operating the device, and memory system including the device

A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.

Non-volatile memory device and method of incrementally programming the same using a plurality of program loops

A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage.

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Changwon-si, South Korea

Hyunjun Yoon