Samsung Electronics Co., Ltd.

Hyunjae Jang

Changwook Jeong

Min-Chul Park

Sanghoon Myung

In Huh

Hyeon Kyun Noh

Hyungtae Kim

Jisu Ryu

Jeonghoon Ko

Yunrong Li

Min Chul Jeon

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Simulation system for semiconductor process and simulation method thereof

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Semiconductor fault analysis device and fault analysis method thereof

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Hwaseong-si, South Korea

Hyunjae Jang