Skhynix Inc.

Hyungsup Kim

Hyung-Sik Won

A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.

Memory device for selectively operating multiple memory groups in different speeds and memory system including the same

A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

Memory device and memory system capable of using redundancy memory cells

A memory system includes a memory device including a memory cell array including a plurality of memory cell groups, and a controller for selectively activating or inactivating one of the memory cell groups.

Memory system for activating redundancy memory cell and operating method thereof

A memory system includes a memory blade including a plurality of operation memories; and a controller coupled to the memory blade, wherein the controller includes: a data base (DB) memory suitable for storing a data base (DB) having first information, which is an average usage amount of an operation memory used for processing a generated target workload, as a field and workloads as an entry; an allocation unit suitable for allocating an usage amount of an operation memory for processing a current target workload based on a value of the first information stored in the DB, corresponding to the current target workload requested to be processed; and a monitor suitable for updating the value of the first information to the average usage amount of the operation memory allocated for processing the current target workload after the processing of the current target workload is completed.

Memory system and operating method thereof

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

A computing device includes: a plurality of memory blades; and a memory blade management unit suitable for controlling each of the plurality of memory blades based on a global map including information of each of the plurality of memory blades, wherein each of the plurality of memory blades includes: a plurality of memory devices; and a controller suitable for detecting a status of each of the plurality of memory devices.

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Yongin, South Korea

Hyungsup Kim