Samsung Electronics Co., Ltd.

Hyungsun Ryu

Wonyoung Seo

Youngcheol Kang

Byeongyong Jeon

Seongkwan Lee

Jaemoo Choi

Hakjung Kim

HakJung Kim

Kangmin Lee

Minho Kang

Cheolmin Park

Shinki Jeong

A testing system for testing an image sensor, includes a probe card, a pogo block receiving output signals of the probe card, an interface board configured to receive output signals of the pogo block, convert the received output signals of the pogo block, and output the converted signals through a cable, and a testing apparatus connected to the interface board through the cable. The testing apparatus is configured to test the device under test through signals received through the cable. The interface board includes an active interface module configured to amplify the received output signals of the pogo block, convert the amplified signals into signals having a same frequency as the received output signals of the pogo block, and transmit the converted signals to the cable.

Interface board for testing image sensor, test system having the same, and operating method thereof

An image sensor test system includes a test device configured to transmit an input signal and a control signal to at least one image sensor through a probe card, and an interface board configured to map the probe card and the test device to each other. The interface board includes a signal receiver configured to receive an image signal from the at least one image sensor, amplify the image signal, and output the image signal to the test device, and the signal receiver includes an operational amplifier configured to amplify the image signal, and a low-frequency attenuator connected to an output terminal of the operational amplifier.

Image sensor test system including operational amplifier and low-frequency attenuator

A tester, which is adapted to test a device under test (DUT), includes a first plurality of signal analysis circuits configured to analyze signals generated by a plurality of DUTs, and a second plurality of signal processing units configured to process the signals analyzed by the first plurality of signal analysis circuits. A switch array is provided, which is electrically coupled between the first plurality of signal analysis circuits and the second plurality of signal processing units. The switch array is configured to electrically connect selected ones of the first plurality of signal analysis circuits with corresponding ones of the second plurality of signal processing units. The number of signal processing units within the second plurality may be less than a maximum number of DUTs that can be connected to the first plurality of signal analysis circuits when the tester is testing a plurality of the DUTs.

Wafer-level multi-device tester and system including the same preliminary class

Display screen or portion thereof with graphical user interface

Growing community of inventors

Yongin-si, South Korea

Hyungsun Ryu