Samsung Electronics Co., Ltd.

HyungSuk Jung

Jonghan Lee

Jaeyeol Song

Sangjin Hyun

Hoonjoo Na

Dongsoo Lee

Wonkeun Chung

Suyoung Bae

Hanjin Lim

Jungmin Park

Wandon Kim

Cheolwoo Park

Jeonghyuk Yim

Seokjun Won

Kwangyul Lee

Jeongeon Lee

Younsoo Kim

Minwoo Song

Jaehyoung Choi

Sunmin Moon

Intak Jeon

Sangyub Ie

Hyeri Hong

A batch-type apparatus for atomic layer etching (ALE), which is capable of ALE-processing several wafers at the same time, and an ALE method and a semiconductor device manufacturing method based on the batch-type apparatus, are provided. The batch-type apparatus for ALE includes a wafer stacking container in which a plurality of wafers are arranged in a vertical direction, an inner tube extending in the vertical direction, a plurality of nozzles arranged in a first outer portion in the inner tube in a horizontal direction, and a heater surrounding the inner tube and configured to adjust a temperature in the inner tube, wherein gas injection holes are formed corresponding to a height of the plurality of wafers in each of the plurality of nozzles, and a gas outlet is formed in a second outer portion in the inner tube, opposite to the first outer portion.

Batch-type apparatus for atomic layer etching (ALE), and ALE method and semiconductor device manufacturing method based on the same apparatus

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

Integrated circuit device

A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

Semiconductor devices

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

Semiconductor device and method of manufacturing the same

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

Semiconductor device having a capping pattern on a gate electrode

Gate electrode having upper and lower capping patterns

A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).

Semiconductor device and method of fabricating the same

Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.

Growing community of inventors

Suwon-si, South Korea

HyungSuk Jung