Samsung Electronics Co., Ltd.

Hyungjung Seo

Sojung Park

Youngrok Choi

A system for verifying an integrated circuit includes a tracing module configured to: trace a specified path based on the specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit and a netlist of the integrated circuit at a transistor level, generate a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declare design constraints for the specified path based on the list of the nets, and generate parasitic data for the net based on the list of the nets. The system further includes an analysis module configured to perform a timing analysis for the specified path based on the design constraints and the parasitic data.

Methods and systems for verifying integrated circuits

A method of operating a computing device for detecting clock domain crossing (CDC) violation in a design of a memory device, the method includes parsing a Netlist to generate a circuit database, parsing a clock tree using the circuit database to generate a clock tree database, extracting a non-toggled point using the clock tree database to generate a false path database based on the non-toggled point, and extracting a CDC violation identified from one or more simulation waveforms using the clock tree database and the false path database.

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Suwon-si, South Korea

Hyungjung Seo