International Business Machines Corporation

Hyungjun Kim

Cyril Cabral, Jr

Stephen Mark Rossnagel

Oleg Gluschenkov

Vijay Narayanan

Dae-Gyu Park

Fenton Read McFeely

Alessandro Cesare Callegari

John Jacob Yurkas

Steffen K Kaldor

Soon-Cheon Seo

Kenneth Parker Rodbell

Supratik Guha

Seyoung Kim

Tayfun Gokmen

Christopher Peter D'Emic

Derren Neylon Dunn

Douglas Andrew Buchanan

Malte Johannes Rasch

Ricky S Amos

Andrew John Kellock

Derren N Dunn

Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array having a set of conductive row wires and a set of conductive column wires intersecting the set of conductive row wires, and optimizable crosspoint devices at intersections of the set of conductive column wires and the set of conductive row wires. A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices in the weight array until all of the crosspoint devices in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint device from the weight array to the reference array.

Alignment techniques to match symmetry point as zero-weight point in analog crosspoint arrays

The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Atomic layer deposition metallic contacts, gates and diffusion barriers

A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO, AlOand other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000&#xb0; C. A low temperature/low pressure CVD technique with Re(CO)as the source material is used when Re is to be deposited.

High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaN, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

Method of forming an interconnect structure diffusion barrier with high nitrogen content

An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MN, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WN, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNlayer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000&#xb0; C.

Temperature stable metal nitride gate electrode

Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaCl). The invention generates a sharp interface between low-k materials and liner materials.

PE-ALD of TaN diffusion barrier region on low-k materials

A method to deposit TaN by plasma enhanced layer with various nitrogen content. Using a mixture of hydrogen and nitrogen plasma, the nitrogen content in the film can be controlled from 0 to N/Ta=1.7. By turning off the nitrogen flow during deposition of TaN, a TaN/Ta bilayer is easily grown, which has copper diffusion barrier properties superior to those of a single Ta layer or a single TaN layer.

Plasma enhanced ALD of tantalum nitride and bilayer

Interconnect structure diffusion barrier with high nitrogen content

Atomic layer deposition of metallic contacts, gates and diffusion barriers

A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250&deg; C. and about 500&deg; C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.

Process of passivating a metal-gated complementary metal oxide semiconductor

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Lagrangeville, NY, United States of America

Hyungjun Kim