Samsung Electronics Co., Ltd.

Hyung Suk Lee

Yun Il Lee

Jae Hyun Park

Sung Il Park

Eun Sil Park

Joong Gun Oh

Dong Hun Lee

Mirco Cantoro

Keon Yong Cheon

Sung Ii Park

Yeon Cheol Heo

Myung-Dong Ko

Eun Shoo Han

Sang Hyeon Lee

Yun Ii Lee

Bong Cheol Kim

Byoung Gi Kim

Seung Chan Yun

Chang Min Yoe

A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.

Semiconductor device having a non-linear gate separation structure

A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

Semiconductor device

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same

A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.

A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.

Semiconductor device including vertical channel

A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.

Semiconductor device and method of fabricating the same

A navigation method, apparatus, and a computer readable medium for a mobile terminal support a display mode that provides a good field of view and enhanced readability. An input signal for enabling a route guidance function is received. Map data for route guidance is outputted when the route guidance function is enabled. Whether to activate a heads-up display (HUD) mode is determined. When the HUD mode is activated, only preset guidance information items that are extracted from the map data are displayed. Hence, the driver does not have to look away from the road to view the map on the screen, significantly reducing the risk of traffic accidents. Simplified route guidance information is provided to solve poor map readability due to screen size limitations of a mobile terminal.

Navigation method and apparatus for mobile terminal

Growing community of inventors

Suwon-si, South Korea

Hyung Suk Lee