Skhynix Inc.

Hynix Semiconductor Inc.

Hyung Soo Kim

Yong Ju Kim

Ic Su Oh

Tae Jin Hwang

Hee Woong Song

Hae Rang Choi

Jae Min Jang

Ji Wang Lee

Sung Woo Han

Chang Kun Park

Kun Woo Park

Jong Woon Kim

Seong Hwi Song

Jun Yong Song

Han Kyu Chi

Jeong Kyoum Kim

Dae Han Kwon

Ki Myung Kyung

Jong Joo Shim

Hee Wong Song

A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.

Interface circuit relating to variable delay, and semiconductor apparatus and system including the same

A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.

Semiconductor device

A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.

Symbol interference cancellation circuit and system including the same

An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

Integrated circuits relating to transmission data and latch clock signals

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Semiconductor memory device having pads

A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals.

Semiconductor device with a sense amplifier unit responsive to a voltage change of input signals and a sense control signal

A semiconductor apparatus including an equalizing unit configured to equalize voltages of a bit line and a bit bar line in response to an equalization signal; a precharge circuit unit configured to supply a voltage to the bit line and the bit bar line in response to first and second precharge signals; and a control unit configured to receive the equalization signal, and generate the equalization signal as the first and second precharge signals according to a control signal.

Semiconductor apparatus

An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

On-die termination circuit

A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal.

Bit line sense amplifier control circuit and semiconductor memory apparatus having the same

The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Domain crossing circuit of a semiconductor memory apparatus

A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.

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Gyeonggi-do, South Korea

Hyung Soo Kim