Skhynix Inc.

Hynix Semiconductor Inc.

Hyung-Sik Won

Hyungsup Kim

Hyung-Sup Kim

Hae-Rang Choi

Sung-Soo Chi

Wan-Jun Roh

A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.

Memory device for selectively operating multiple memory groups in different speeds and memory system including the same

A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

Memory device and memory system capable of using redundancy memory cells

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Memory system

A memory system includes a memory device including a memory cell array including a plurality of memory cell groups, and a controller for selectively activating or inactivating one of the memory cell groups.

Memory system for activating redundancy memory cell and operating method thereof

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

A converged memory device includes at least a first memory and a second memory and a controller to select the first or second memory for performing fast or normal data processing, respectively, in response to a request from a host. The first memory includes a sense amplifier, one or more cell matrices, and a switching device. The cell matrices includes one or more first region memory cells disposed less than a first distance from the sense amplifier and one or more second region memory cells disposed more than a second distance from the sense amplifier, the second distance being longer than the first distance. The switching device is disposed between the first and second region memory cells. The controller controls the switching device to couple the first region memory cells to the sense amplifier and to decouple the second region memory cells from the sense amplifier according to the request.

Converged memory device and method thereof

A converged memory device includes: a first memory installed in an environment having a first temperature; a second memory installed in an environment having a second temperature that is lower than the first temperature; and a controller configured to selectively access the first memory or the second memory in response to a request.

Converged memory device and operation method thereof

A memory device includes a plurality of memory cells, a weak address storage block suitable for storing a weak address of a weak cell of which data retention time is shorter than a reference time, among the plurality of memory cells, a refresh counter suitable for generating a counting address, and an address selection block suitable for outputting a refresh address by selecting one of the counting address and the weak address, wherein, in selecting the counting address, the address selection block selects the weak address for a predetermined period, when a value of at least one preset bit of the counting address is changed.

Memory device

Memory system and operating method thereof

A semiconductor device may include: a conversion value generator suitable for detecting first and second transition factors that are independent of each other, and generating first and second conversion values corresponding to the first and second transition factors, respectively; and a signal converter suitable for generating an output signal by reflecting the first and second conversion values into an input signal.

Semiconductor device, semiconductor memory device and communication system

A memory device may include: a cell array comprising a main area and an adjacent area with a plurality of main memory cells disposed in the main area and a plurality of adjacent memory cells disposed in the adjacent area; a control circuit suitable for controlling a row operation and column operation of the cell array; and an adjacent area controller suitable for controlling adjacent memory cells so that the adjacent memory cells are operated under a different condition from the main memory cells.

Memory device and method for operating the same

A memory device may include a cell array including a plurality of memory cells and a bit line coupled to the plurality of memory cells; a sense amplifier suitable for amplifying a voltage difference between a first line and a second line; and a separation unit suitable for electrically coupling the bit line and the first line, and electrically separating the bit line and the first line during an initial period of an operation of the sense amplifier.

Memory device and operation method thereof

A driver includes a driving block suitable for driving a data transferred through a first signal line to a second signal line, a first precharge unit suitable for precharging the second signal line with a first driving power during a first precharge operation; and a second precharge unit suitable for precharging the second signal line with a second driving power which is different from the first driving power during a second precharge operation performed subsequent to the first precharge operation.

Driver and semiconductor memory device including the same

A sense amplifier includes a first inverter having an input terminal connected to a first line and an output terminal connected to a second line, and a second inverter having an input terminal connected to the second line and an output terminal connected to the first line, wherein an NMOS transistor of the first inverter and an NMOS transistor of the second inverter have well biases different from each other.

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Cheongju, South Korea

Hyung-Sik Won