Skhynix Inc.

Hynix Semiconductor Inc.

Hyung Sik Won

Tae Hun Kim

Jae Jin Lee

Young Jung Choi

Chang Hyun Kim

Eui Cheol Lim

Sun Woong Kim

Seung Han Oak

Jun Phyo Lee

Hae Rang Choi

Kee Teok Park

Hyun Ju Ham

Hong Jung Kim

Myoung Jin Lee

A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Memory system

A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Semiconductor device with memory banks and sense amplifier arrays

A multi-level sensing circuit for a multi-level memory device configured to 'recognize' more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage.

Multi-level sensing circuit and semiconductor memory device including the same

A memory system includes a memory controller configured to generate a memory control signal for controlling a read operation or a write operation of data, and a plurality of memory devices configured to perform the read operation or the write operation in response to the memory control signal. A first memory device stores a first number of data received from the memory controller, and a second memory device receives a second number of data corresponding to a specific number of data from among the first number of data, copies the second number of data to generate a third number of data, and stores the third number of data in the second memory device.

Memory system capable of transmitting data directly between memory devices

A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.

Semiconductor device

Semiconductor device for compensating offset of sense amplifier

Multi-level sensing circuit configured to use a bit line charge

A semiconductor memory device includes a sense amplifier, a voltage supply circuit and a voltage supply control circuit. The sense amplifier may be activated by receiving driving voltages from first to third voltage supply lines to detect and amplify voltage levels of a data line and a data bar line. The voltage supply circuit may apply the driving voltages to the first to third voltage supply lines in response to first to third voltage supply signals and a bias control signal. The voltage supply control circuit may generate the first to third voltage supply signals and the bias control signal in response to an active signal.

Semiconductor memory device

A semiconductor memory device includes a sense amplifier control circuit configured to generate a first sense amplifier driving voltage application signal, a second sense amplifier driving voltage application signal and a third sense amplifier driving voltage application signal in response to an active signal, a precharge signal and a write pulse; and a sense amplifier driving voltage providing circuit configured to provide driving voltages to a sense amplifier through first and second driving voltage application lines during enable periods of the first to third sense amplifier driving voltage application signals.

Semiconductor memory device with sense amplifier that is selectively disabled

A semiconductor device may be provided. The semiconductor device may include a memory area. The memory area may be configured to compare an address with a first failure address and a second failure address to store an input datum into a redundancy area and to output the stored input datum as an output datum or configured to compare the address with the first and failure addresses to correct an error of an input datum stored in a normal area to output the corrected input datum as the output datum. The semiconductor device may include a failure address storage circuit. The failure address storage circuit may be configured to store the address as a first failure address based on a first retention information signal and configured to store the address as a second failure address based on a second retention information signal.

Semiconductor devices and semiconductor systems including the same

A voltage generation apparatus may include an external voltage sensing circuit configured to generate a first start signal and a second start signal by sensing the magnitude of a first external voltage and the magnitude of a second external voltage. The voltage generation apparatus may include an internal voltage sensing circuit configured to generate a voltage generation signal by comparing an internal voltage with a target voltage. The voltage generation apparatus may include a voltage pumping circuit configured to be activated in response to the first start signal, configured to perform a pumping operation based on the voltage generation signal, and configured to generate the internal voltage. The voltage generation apparatus may include a voltage regulating circuit configured to be activated in response to the first and second start signals, and configured to generate the internal voltage based on the voltage generation signal.

Growing community of inventors

Cheongju-si, South Korea

Hyung Sik Won