Hynix Semiconductor Inc.

Skhynix Inc.

Other

Gumyoung General Co., Ltd.

Hyung Seok Kim

Min Kyu Lee

Seok Jin Joo

Kyung Pil Hwang

Ju In Kim

Keum Hwan Noh

Sook Kyung Kim

Jong Hyun Park

Tae Geun Kim

HakKi Han

Noh Yong Park

Mu Jung Lee

Gum-Gee Lee

Woo Won Youn

Ju Dae Kim

The present disclosure relates to an elevator having a function of removing dust adhered to an object aboard, including: a car which provides a boarding space, and in which a pair of air holes disposed in a diagonal direction each other at a same height of an inner space are formed; and a pair of fan modules that generates whirlwind rotating in the inner space of the car by ejecting air traveling from one of the pair of air hoes in a direction away from a center of the inner space of the car and ejecting air traveling from the other of the pair of air hoes in a direction away from the center of the inner space of the car, in which dust adhered to the object aboard inside the car is separated from the object aboard by the whirlwind generated inside the car.

Elevator having function of removing dust adhered to object aboard

A balancing weight composition with excellent extrudability is provided. More specifically, the balancing weight composition includes a stainless steel and a resin base, wherein the resin base includes a polyester-based engineering plastic, an epoxy resin and an ionically cross-linked elastomer at a suitable content ratio to improve extrusion flowability, flexural strength and adhesive strength of a molded material.

Balancing weight composition with excellent extrudability

A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.

Semiconductor memory device having improved erase characteristic of memory cells and erase method thereof

A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period.

Semiconductor memory device and method of operating the same

A semiconductor memory device and a method of operating the same include a circuit group configured to apply a program maintaining voltage between the program prohibition voltage and the program permission voltage to bit lines connected to programmed memory cells to prevent a decrease in threshold voltage.

A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.

A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The selected MLCs are pre-programmed with a pre-program (first) voltage; and the remaining MLCs are prohibited from pre-programming; then the remaining MLCs connected to the selected word line are programmed by applying a program (second) voltage that gradually rises from the pre-program voltage at a ratio of a step voltage n for the selected line.

Program method of flash memory device

Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Erase method of flash memory device

Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Growing community of inventors

Seoul, South Korea

Hyung Seok Kim