Electronics and Telecommunications Research Institute

Hyung-Moo Park

Chang-Seok Lee

Sin-Chong Park

Hyung-Jin Yoon

Seong-Su Park

Dong-Goo Kim

Min-Kyu Song

Gyeong-Lyong Park

Min-Gun Kim

Seung-Goo Kang

Jae-Kyoung Mun

Hae-Cheon Kim

Jong-Lam Lee

Choong-Hwan Kim

Ki-Hong Kim

Chul-Soon Park

Jin-Hee Lee

Sang-Soo Choi

Sung-Jae Maeng

Hyung-Jun Yoo

Hyung-Sup Youn

In-Gab Hwang

In-Gap Whang

Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation layer; selectively etching the first SiN layer so as to expose top surfaces only of the source and drain electrodes; plating a gold layer only on the source and drain electrodes; depositing a second SiN layer over the first SiN layer and the gold layer; and forming a gold coating layer on a rear surface of the substrate. In the device, parasitic carriers in interface between the substrate and the first undoped GaAs buffer layer can be prevented from being introduced into the channel layer by the superlattice layer during operation of the device.

GaAs power semiconductor device operating at a low voltage and method

An analog/digital dual-mode power amplifier which provides a good linearity and a high efficiency comprises a first and a second power field effect transistors, and an input stage, a middle stage and an output stage. An input stage receives the input signal through an input terminal. A middle stage applies a second gate bias voltage appropriately controlled in response to an analog operating mode or a digital operating mode to a second power FET. An output stage provides matching at center frequency and has the impedance of less than 2.OMEGA. for a second harmonic and a third harmonic. Accordingly, a good linearity and high efficiency circuit can be obtained.

Gaas power amplifier for analog/digital dual-mode cellular phones

A method for making a T-shaped gate of a field effect transistor is disclosed. The method includes the steps of sequentially depositing first and second photoresist layers on a semiconductor substrate and performing an exposure using electron beams having different energy, one of the electron beams having a first energy to lightly expose only the second photoresist layer and the other of the electron beams having a second energy to lightly expose all of the first and second layers. The invention reduces gate resistance and parasitic capacitance of the T-shaped gate.

Method for making T-gate of field effect transistor

A low noise amplifier of the present invention may be useful to a portable cellular phone or a microwave communication system, particularly to a monolithic circuit in which the amplifier includes an input impedance component consisting of capacitors and an inductor, two MESFETs in a cascade connection and a capacitor connected between the two MESFETs so as to enhance the stability of the amplifier when a node strapping a plurality of ground terminals of the amplifier is connected to an external circuit by means of a bonding wire.

Low noise amplifier in monolithic integrated circuit

Method of making a gaAs power semiconductor device operating at a low

A package for a power semiconductor device is made using the method comprising the steps of preparing a lead frame including a blade or paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus. The method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

Package for a power semiconductor device

A micro light valve which is corresponding to each of pixels for display and which passes or shuts a light beam by electrostatic force to display images, said light valve comprising a data electrode formed on a substrate and connected with each of data lines through a via; a selection electrode formed on the substrate and connected with each of selection lines; a common electrode formed between the selection and data electrodes; a flat-shaped micro shifting element capable of moving in linear direction and which serves as a resistance body; insulating layers formed respectively between the shifting element and each of the electrodes; a frame for serving as a black matrix, which has a guiding means for guiding the shifting element; and the three electrodes for receiving externally applied driving signals to drive the shifting element and which serve as stationary elements with three phases.

Micro light valve and method for manufacturing the same

Disclosed is a switch circuit which has a depletion mode n-channel MOSFET which can be used in a circuit allowing only a positive voltage to be supplied thereto, comprising a first D-FET having a gate for receiving an input signal, a drain for outputting an output signal and a source; a first resistor connected between the drain of the first D-FET and a positive voltage source to bias the drain of the first D-FET; a second D-FET having a gate connected to an intermittence controlling voltage source, a drain and a source connected to the positive voltage source and the source of the first D-FET 201, respectively; a second resistor connected between the gate of the second D-FET and a ground to bias the gate of the second D-FET; a constant-current source connected between each of the sources of the first and second D-FET and the ground; a bypass capacitor connected in parallel with the constant-current source and between the drain of the constant-current source and the ground to bypass an RF signal to the ground; and a third resistor connected between the gate of the first D-FET 201 and the ground to bias the gate of the first D-FET. Since the switch circuit can be operated only by a positive voltage without use of a negative voltage, it can be embodied with a general depletion mode n-channel MOSFET which can be fabricated by a relatively simple fabrication sequence and has a relatively simple structure in comparison with an enhancement mode n-channel MOSFET.

Switch circuit for monolithic microwave integrated circuit device

A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

Method of packaging a power semiconductor device

A method is disclosed for manufacturing a very fast micro light valve of the type used to control the passage of light through a pixel. The method comprises preparing a substrate, which can be made of glass, and forming transparent electrodes on the main surface of the substrate. Next an insulating layer is deposited on the substrate and a first sacrificial layer is formed on the insulating layer. A pattern shifting element layer is formed on the first sacrificial layer and a second sacrificial layer is formed on the substrate and provided with a shifting element layer. After portions of the sacrificial layers are removed by etching to form a frame contact portion, a patterned frame layer is formed on the frame contact portion. Then a frame and a shifting element capable of moving in the frame under an applied external electrostatic force are formed by removing the remaining sacrificial layers.

Method for manufacturing a micro light valve

There is disclosed a semiconductor device having a plurality of chips in which a predetermined extended addresses are allocated for each of the chips to select the chips in a multiple-chip module, the device comprising: a plurality of semiconductor chip selectors equipped in said semiconductor device, for supplying an internal chip select signals to select the chips in response to said extended addresses and a module select signal; and each of said semiconductor chip selectors having a plurality of decoders for receiving the extended addresses and outputting a predetermined logic signal, and an AND gate for receiving said module select signal and said logic signal of each of said decoders and outputting said internal chip select signals. Accordingly, in packaging semiconductor chips in accordance with the invention, a semiconductor chip module can be miniatured more, processing steps of such semiconductor chip module can be reduced, and input and output terminals of such semiconductor chip module can be reduces in the number so that the invention can improve access time or delay time in the module.

Growing community of inventors

Daejeon, South Korea

Hyung-Moo Park