Hyundai Electronics Industries Co. Ltd.

Hyung Ki Kim

Jong Wook Lee

The present invention discloses a method for fabricating a SOI wafer. The method for fabricating the SOI wafer of the present invention, comprising the steps of: preparing a semiconductor substrate and a base substrate; forming a pad oxide layer, a nitride layer and a mask oxide layer in sequence on one surface of the semiconductor substrate; etching the pad oxide layer, the nitride layer, and the mask oxide layer to expose an isolation region of the semiconductor substrate; forming a trench by etching the exposed semiconductor substrate region; removing the mask oxide layer; forming a field oxide layer having bird's-beak at the edge thereof by oxidizing the low surface of the trench; removing the field oxide layer; forming an isolation layer of trench type to fill the oxide layer into the trench; removing the nitride layer and the pad oxide layer; depositing a first insulating layer on the isolation layer and the semiconductor substrate; depositing a second insulating layer on the base substrate; bonding the semiconductor substrate and the base substrate to form a contact of the first insulating layer with the second insulating layer; polishing the surface of the semiconductor substrate using the isolation layer as a polishing stopper; and further polishing the surface of the semiconductor substrate to expose the bird's beak and to form a semiconductor layer of a desired thickness.

Method of fabricating SOI wafer

A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.

SOI device with double gate and method for fabricating the same

Disclosed is a semiconductor device having low voltage characteristic and advantageous integrity simultaneously. The semiconductor device comprises a silicon-on-insulator (SOI) substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; and a first transistor and a second transistor formed on the active region of the SOI substrate, wherein the first and second transistors are formed as a stack structure on one active region and they share one gate electrode, a drain region of the second transistor is electrically connected to the gate electrode and a source region of the second transistor is electrically connected to the active region.

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Inchon, South Korea

Hyung Ki Kim