Sungkyunkwan University

Anapass Inc.

Skaichips Co., Ltd.

Hyung Ki Huh

Kang Yoon Lee

Young Gun Pu

Jong Wan Jo

Dong Joon Lee

Yeon Jae Jung

Joon Mo Yoo

Dong Gyun Kim

Jae Bin Kim

Sung June Byun

Dae Young Choi

Seok Kee Kim

Sung Jun Byun

Disclosed are an artificial intelligence algorithm-based wireless power transmitter, wireless power receiver, and wireless power charging system that are capable of high-speed response to environmental changes and that can optimize the power efficiency of a wireless power receiver, estimate a dynamic location from a signal received from the wireless power receiver using artificial intelligence technology, and dynamically transmit wireless power to a prioritized wireless power receiver according to a power state.

Artificial intelligence algorithm-based wireless charging system capable of high-speed response to environmental changes

Provided are a scalable analog passive intermodulation (PIM) module, a method of controlling analog PIM, a signal processing circuit, and a sensor device. The scalable analog PIM module includes a first plural number of digital-to-analog converters (DACs), a first plural number of static random access memory (SRAM) calculators connected to the first plural number of DACs, at least one analog-to-digital converter (ADC) connected to the first plural number of SRAM calculators and configured to convert an analog convolution result signal into digital convolution data, and an analog PIM controller configured to output an enable control signal for enabling a second number, which is equal to or less than first plural number, of SRAM calculators among the first plural number of SRAM calculators to the first plural number of SRAM calculators on the basis of the convolution data output from the ADC.

Scalable analog PIM module, method of controlling analog PIM, signal processing circuit, and sensor device

Disclosed is a phase-locked loop which alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal. When the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a memory device.

Phase-locked loop and delay-locked loop

Disclosed is a phase-locked loop and a delay-locked loop. When the phase-locked loop switches from a sleep state to an active state, a frequency of a reference signal is the same as a frequency of a reference signal which has been synchronized in a previous active state. The phase-locked loop alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal, when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a capacitor.

Growing community of inventors

Seoul, South Korea

Hyung Ki Huh