Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Semes Co., Ltd.

Kia Motors Corporation

Hyung Joon Kim

Han Bit Kim

Yun Tae Lee

Min Cheol Park

Jong Ho Lee

Jong Hoon Kim

Bio Kim

Jung Ho Kim

Dae Bok Oh

Seung Pyo Lee

Sang Jong Lee

Min Gon Lee

Byoung Hwa Lee

Sung Tae Kim

Jae Yeol Choi

Yong-Hoon Son

Kang Heon Hur

Hyun Jung Lee

Yong-Suk Tak

Yujin Kim

Sang Heon Lee

Hyung Suk Kim

Jung Ho Shim

Jae Young Ahn

Sang Huk Kim

Hanmei Choi

Dae Hyun Park

Eun Jung Jo

Hae Suk Chung

Ji Hun Kim

Ji Won Kim

Seok Hwan Kim

Ji Hoon Choi

Phil Ouk Nam

Ki Yong Lee

Jung Hyun Cho

Won Kyu Jeung

Min-Seok Kim

Jae Hyun Lim

Jung-Woo Kim

Jeong Yun Lee

Seulye Kim

Sung Wook Kim

Tae Ho Yun

Min-seok Kim

Eun Yeoung Choi

Yong Seok Cho

Su Hyeong Lee

Jun Hee Kim

Jung Geun Jee

Jong Gun Lee

Hyun Ju Kim

Han Kyung Bae

Duk Hyun Son

Junggeun Jee

Se Joo Kim

Ju Myung Suh

Hyungchul Moon

Jang Ho Lee

Guen Hong Lee

Kyoung Ae Kim

Eunyeoung Choi

Young Seon Son

Hyung Je Woo

Seung Kue Kim

Su Jin Shin

Ju Mi Yun

Sung Hae Lee

Joong Yun Ra

Chul Seung Lee

Ji Yoon Park

Mi Ja Han

Hong Suk Kim

Seong Hee Choi

Sung Dae Cho

Yoon Seok Seo

Kongsoo Lee

Jung Woo Sung

Kyung Yub Jeon

Dae Kyu Shin

Sung Gil Kim

Hae Sock Chung

Vasily Pashkovskiy

Tae Ho Song

Won Jin Baek

Teawon Kim

Seong Hwan Lee

Hyung Sung Kim

Hyun Sang Kwak

Yurim Kim

Byung Kwon Yoon

Chi Hyeon Jeong

Sigwan Kim

Kong Soo Lee

Kang Rae Ha

Sang Jean Jeon

Heung Ki Lee

Hoo Hyoung Lee

Sung Il Jo

A plasma processing apparatus using a magnetic field includes a reaction chamber, a plasma generating device connected to the reaction chamber to generate plasma in the reaction chamber, a substrate support disposed in a lower portion in the reaction chamber to support a wafer to be etched by the plasma, and a magnetic module including a permanent magnet and an electromagnet disposed vertically above the reaction chamber and a DC power supply unit connected to the electromagnet to input power to the electromagnet.

Plasma processing apparatus and plasma control method using magnetic field

A method of manufacturing a susceptor includes preparing an electrostatic chuck (ESC) and a base plate, each including a gas channel, preparing a bush-filter assembly disposed between the gas channel in the ESC and the gas channel in the base plate, and coupling the ESC to the base plate in such a manner that a portion of the bush-filter assembly is accommodated in a first accommodation part formed in a surface of the ESC and that a remaining portion of the bush-filter assembly is at least partially accommodated in a second accommodation part formed in a surface of the base plate.

Susceptor and method of manufacturing the same

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a housing having a treating space treating a substrate; a support unit supporting the substrate at the treating space; a gas supply unit supplying a process gas into the treating space; and a plasma source generating a plasma from the process gas, and wherein the support unit comprises: a dielectric plate placing the substrate on a top surface thereof; a top ring surrounding a circumference of a substrate placed on the dielectric plate; a temperature sensor measuring a temperature of the top ring; a first lifting/lowering member lifting/lowering the top ring; and a controller, and wherein the controller controls the first lifting/lowering member to change a height of the top ring according to an etching amount of the top ring calculated based on the temperature of the top ring measured by the temperature sensor.

Support unit, apparatus for treating substrate with the same

Disclosed is a semiconductor device comprising an oxide semiconductor layer on a substrate and including a first part and a pair of second parts that are spaced apart from each other across the first part, a gate electrode on the first part of the oxide semiconductor layer, and a pair of electrodes on corresponding second parts of the oxide semiconductor layer. A first thickness of the first part of the oxide semiconductor layer is less than a second thickness of each second part of the oxide semiconductor layer. A number of oxygen vacancies in the first part of the oxide semiconductor layer is less than a number of oxygen vacancies in each second part of the oxide semiconductor layer.

Oxide semiconductor device comprising oxygen vacancies

A substrate processing apparatus is provided. The substrate processing apparatus includes: a chuck member; a ceramic puck disposed on the chuck member; a focus ring disposed to surround the ceramic puck; an insulating layer disposed below the focus ring to surround the chuck member; and two electrodes formed in the insulating layer, wherein a distance between the two electrodes is adjustable to form a variable capacitance.

Variable capacitance device, substrate processing apparatus including the variable capacitance device, and substrate processing method

A semiconductor device includes a conductive line that extends in a first direction on a substrate, a first oxide semiconductor layer, including a first crystalline oxide semiconductor material containing a first metal element, on the conductive line, a second oxide semiconductor layer, which is in physical contact with the first oxide semiconductor layer and is connected to the conductive line, on the conductive line, a gate electrode that extends in a second direction, which crosses the first direction, on a side of the second oxide semiconductor layer, and a capacitor structure connected to the second oxide semiconductor layer on the second oxide semiconductor layer and the gate electrode, wherein the second oxide semiconductor layer includes a second crystalline oxide semiconductor material containing the first metal element and second and third metal elements, which are different from the first metal element.

Semiconductor device and method for fabricating the same

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a housing having a treating space for treating a substrate; a support unit configured to support the substrate at the treating space; and a plasma source for generating a plasma from a process gas supplied into the treating space; an exhaust line connecting to the housing and exhausting an atmosphere of the treating space; and a pressure adjusting unit positioned between the support unit and the exhaust line and configured to adjust an exhaust pressure exhausted from the exhaust line, and wherein the pressure adjusting unit includes: an opening/closing member for opening and closing the exhaust line; a lifting/lowering member for moving the opening/closing member in an up/down direction; and an elastic member for providing a restoring force to the lifting/lowering member.

Apparatus for treating substrate and method for treating a substrate

A multilayer capacitor includes: a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately laminated in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and respectively disposed on first and second surfaces of the body, the first and second surfaces opposing each other. The body further includes a first via electrode, connecting the at least one first internal electrode and the first external electrode to each other in the first direction, and a second via electrode connecting the at least one second internal electrode and the second external electrode to each other in the first direction.

Multilayer capacitor and board having the same embedded therein

Provided is a substrate supporting apparatus with improved durability. The substrate supporting apparatus includes a body configured to support a substrate and formed of a dielectric substance; a heat transfer medium supply hole installed to penetrate the body; a first electrostatic electrode disposed in the body; and a second electrostatic electrode disposed in the body, located on the first electrostatic electrode, and electrically connected to the first electrostatic electrode.

Substrate supporting apparatus and substrate treating apparatus including the same

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

Semiconductor memory device

A multilayer capacitor includes a capacitor body including a dielectric layer and first and second internal electrodes and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, first and second side portions disposed on the fifth and sixth surfaces of the capacitor body, respectively, and first and second external electrodes disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively. The first and second internal electrodes have protrusions at one-side edge in a direction perpendicular to the fifth and sixth surfaces of the capacitor body.

Multilayer capacitor and board having the same mounted thereon

A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Vertical-type memory device

A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

Method of manufacturing three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns

A multilayer capacitor includes: a capacitor body including first and second dielectric layers, internal electrodes, and including first to six surfaces; first and second external electrodes disposed on the third and fourth surfaces, respectively; and third and fourth external electrodes disposed on the fifth and sixth surfaces, respectively. The internal electrodes include: first internal electrode disposed on the first dielectric layer, having both ends connected to the first and second external electrodes, respectively, and having a hole; a second internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode and be connected to the third external electrode; and a third internal electrode disposed on the second dielectric layer so as to overlap a portion of the first internal electrode, be spaced apart from the second internal electrode, and be connected to the fourth external electrode.

Multilayer capacitor and board having the same

Growing community of inventors

Suwon-si, South Korea

Hyung Joon Kim