Avago Technologies International Sales Pte. Limited

Hyung-Joon Jeon

Jun Cao

Delong Cui

Anand Jitendra Vasani

Seong-Ho Lee

Yonghyun Shim

Wei Zhang

Angus Tang

Seong Ho Lee

SangHye Chung

Vadim Milirud

In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.

Wide frequency range high speed clock multiplexer

A system includes a sampler, a receiver phase-locked loop circuit configured to provide one or more input clock signals, and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler. The phase interpolation circuit further includes a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code, and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal, wherein the outputs of the first phase interpolator and second phase interpolator are configured to be merged.

Variation tolerant linear phase-interpolator

An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine integral non-linearity of the phase interpolator at the first code based on the total delay. The control logic may further calibrate a first code of a phase interpolator based, at least in part, on the integral non-linearity.

INL detection and calibration for phase-interpolator

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Hyung-Joon Jeon