Electronics and Telecommunications Research Institute

Hyung-Jin Yoon

Hyung-Moo Park

Min-Kyu Song

Dong-Goo Kim

Seong-Su Park

Sin-Chong Park

Seung-Goo Kang

Chang-Seok Lee

Ki-Hong Kim

Chul-Soon Park

Gyeong-Lyong Park

A package for a power semiconductor device is made using the method comprising the steps of preparing a lead frame including a blade or paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus. The method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

Package for a power semiconductor device

A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

Method of packaging a power semiconductor device

A flat display device has a plurality of pixels and a plurality of micro light valves which correspond to each of the pixels thereof, and has a plurality of selection lines and data lines disposed in a matrix the micro light valves each comprise a data electrode to be connected with each of the data lines through a via, a selection electrode to be connected with each of the selection lines, a common electrode formed between the selection and data electrodes, a frame, and a shifting element capable of being moved in the frame by driving signals to be applied to the data and selection electrodes, so as to pass or shut off a light beam. A first driving means is connected to the respective selection lines, for supplying a predetermined selection signal for said light valves; and a second driving means is connected to the respective data lines, for supplying a predetermined data signal for said light valve.

Flat display device and method for manufacturing the same

There is disclosed a semiconductor device having a plurality of chips in which a predetermined extended addresses are allocated for each of the chips to select the chips in a multiple-chip module, the device comprising: a plurality of semiconductor chip selectors equipped in said semiconductor device, for supplying an internal chip select signals to select the chips in response to said extended addresses and a module select signal; and each of said semiconductor chip selectors having a plurality of decoders for receiving the extended addresses and outputting a predetermined logic signal, and an AND gate for receiving said module select signal and said logic signal of each of said decoders and outputting said internal chip select signals. Accordingly, in packaging semiconductor chips in accordance with the invention, a semiconductor chip module can be miniatured more, processing steps of such semiconductor chip module can be reduced, and input and output terminals of such semiconductor chip module can be reduces in the number so that the invention can improve access time or delay time in the module.

Semiconductor device having a decoding circuit for selection chips

Growing community of inventors

Daejeon, South Korea

Hyung-Jin Yoon