Skhynix Inc.

Hynix Semiconductor Inc.

Applied Materials, Inc.

Lg Display Co., Ltd.

Hyung Jin Park

Sanjeev Baluja

Bok Hoen Kim

Xinhai Han

Praket Prakash Jha

Michael Wenyoung Tsiang

Mayur G Kulkarni

Won Ho Shin

Sang Hyuk Kim

Ryeun Kwan Kim

Jason K Foster

Majid K Shahreza

Jin Chul Son

Saiprasanna Gnanavelu

Myung Hun Ju

Je Hyun Kim

Jung Wook Kim

Hyo Jun Lee

Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.

Semiconductor device

Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

VNAND tensile thick TEOS oxide

A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region.

Variable resistance device having parallel structure

A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to first and second channel layers formed on sidewalls and upper portions of a plurality of gates, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; the gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; and a second plug coupled to the second channel layer.

Method for manufacturing semiconductor device with first and second gates over buried bit line

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

A semiconductor device with a copper line comprises a lower portion of a copper pattern buried in an interlayer insulating film, an upper portion of the copper disposed over the upper portion of the lower copper pattern, and an upper barrier metal layer disposed over upper and side surfaces of the upper copper pattern. As a result, the copper pattern is protected by the barrier metal layers, providing a metal line with a stable structure.

Semiconductor device with a copper line and method for manufacturing the same

Semiconductor device with vertical channel over buried bit line

A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern. The conductive polymer layer includes a nano-sized metal powder and a polymer.

Semiconductor device and method for fabricating the same

A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.

Fuse of semiconductor device

A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.

Fuse of semiconductor device and method for manufacturing the same

A method for cutting a liquid crystal display panel includes transferring a pair of attached mother substrates having a plurality of panel regions arranged thereon to a first scribing part; forming first prearranged cut lines for sectioning the panel regions in a first direction on front and rear surfaces of the mother substrates through a first scribing unit having a plurality pairs of first heads; forming second prearranged cut lines for sectioning the panel regions in a second direction on the front and rear surfaces of the mother substrates through a second scribing unit having a plurality pairs of second heads; and transferring the mother substrates with the first and second prearranged first and second cut lines formed thereon to a breaking part and separating them into a plurality of unit liquid crystal display panels.

Growing community of inventors

Icheon, South Korea

Hyung Jin Park