Intel Corporation

Hyung-Jin Lee

Telesphor Kamgaing

Georgios C Dogiamis

Gilbert W Dewey

Aleksandar Aleksov

Henning Braunisch

Cho-Ying Lu

Richard J Dischler

Said Rami

Ian A Young

Mark Armstrong

Saurabh Morarka

Nathaniel August

Carlos Nieva-Lozano

Johanna M Swan

Adel A Elsherbini

Bernhard Sell

Kinyip Phoa

Jeff C Morriss

Ayan Kar

Matthias Eberlein

Sachin Kalia

Ajay Balankutty

Satwik Patnaik

Guannan Liu

Qiang Yu

Ram Sadhwani

Peter Tsugio Kurahashi

Triveni Suryakant Rane

Gerogios Dogiamis

Surej Ravikumar

An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

FinFET varactor quality factor improvement

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

Non-planar integrated circuit structures having asymmetric source and drain trench contact spacing

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

Integration of III-V transistors in a silicon CMOS stack

Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

Through-substrate waveguide

Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Field-effect transistors with asymmetric gate stacks

Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.

Package with side-radiating wave launcher and waveguide

Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

Single side band transmission over a waveguide

Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.

Semiconductor package comprising chiplets disposed on a substrate which are electromagnetically coupled by dielectric waveguides and a computing networks formed therefrom

There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

Electromagnetic wave launcher including an electromagnetic waveguide, wherein a millimeter wave signal and a lower frequency signal are respectively launched at different portions of the waveguide

A voltage controlled oscillator (VCO) circuit is disclosed. The VCO circuit comprises a VCO tuning circuit comprising a primary inductive coil. In some embodiments, the VCO tuning circuit is configured to generate a VCO output signal at a first resonance frequency. The VCO circuit further comprises a filter circuit comprising a secondary inductive coil. In some embodiments, the filter circuit is configured to resonate at a second, different, resonance frequency, in order to filter a noise associated with the VCO tuning circuit. In some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are concentrically arranged with respect to one another. Further, in some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are magnetically decoupled with respect to one another.

Magnetically decoupled concentric coils structure for area optimized high performance LC VCOs

Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.

Waveguide and transceiver interference mitigation

There is disclosed in one example a communication apparatus, including: an analog data source; a digital communication interface; and an analog-to-digital converter (ADC) circuit assembly, including: an analog sample input; an input clock to provide frequency f; a time-interleaved front end to interleave n samples of the analog sample input; and an ADC array including n successive-approximation register (SAR) ADCs, the SAR ADCs including self-clocked comparators and configured to operate at a frequency no less than 

High-speed analog-to-digital converter

Embodiments herein may relate to an interconnect that includes a transceiver, where the transceiver is configured to receive a data stream, convert the data stream to a quadrature amplitude modulation (QAM) mapping/shaping signal, where the QAM mapping/shaping signal is a frequency component of the data stream, convert the QAM mapping/shaping signal to a Hilbert transform signal, where the Hilbert transform signal includes a reverse order of an in-phase component of the QAM mapping/shaping signal and a reverse order of a quadrature component of the QAM mapping/shaping signal, convert the Hilbert transform signal to a QAM mapping/shaping signal, where the QAM mapping/shaping signal is a single sideband (SSB) time domain mm wave signal, where the SSB time domain mm wave signal is the Hilbert transform signal converted to a time domain signal, and communicate the SSB time domain mm wave signal over a waveguide using a waveguide interconnect.

Orthogonal frequency division multiplexing single sideband transmission over a waveguide

An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

Apparatus and method for single temperature subthreshold factor trimming for hybrid thermal sensor

Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.

Growing community of inventors

Portland, OR, United States of America

Hyung-Jin Lee