Samsung Electronics Co., Ltd.

Hyung-Ik Lee

Sung Heo

Yong-Koo Kyoung

Si-Young Choi

Ki-Hyun Hwang

Han-Mei Choi

Jin-bum Kim

Eun-ha Lee

Dong-Chul Yoo

Ki-hong Kim

Byong-Ju Kim

Ki-Hong Kim

Kyu Sik Kim

Young-Pil Kim

Woo-sung Jeon

Gyeongsu Park

Dongjin Yun

Satoh Ryuichi

Jung-Yun Won

In-sun Jung

Seong Heon Kim

Chan-Hee Park

An optoelectronic device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode, and a buffer layer between at least one of the photoelectric conversion layer and the first electrode, and the photoelectric conversion layer and the second electrode, the buffer layer including one of MoO(2.58&#x2266;x1&#x3c;3.0), ZnO(1.0&#x2266;x2&#x3c;2.0), TiO(1.5&#x2266;x3&#x3c;2.0), VO(1.5&#x2266;x4&#x3c;2.0), TaO(1.0&#x2266;x5&#x3c;2.5), WO(2.0&#x3c;x6&#x3c;3.0), and a combination thereof.

Optoelectronic device, and image sensor and electronic device including the same

A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.

Method of fabricating semiconductor device including a recessed channel

A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.

Memory device and method of fabricating the same

Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.

Semiconductor integrated circuit device and method of fabricating the same

Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.

Semiconductor devices having Si and SiGe epitaxial layers

Growing community of inventors

Suwon-si, South Korea

Hyung-Ik Lee