Samsung Electronics Co., Ltd.

Hyung-gil Baek

Yun-Rae Cho

Sun-dae Kim

Nam-gyu Baek

Sang-Wook Park

Yong-hwan Kwon

Tae-Je Cho

Hyun-Soo Chung

Young-jae Kim

Joong-Hyun Baek

Seung-Kwan Ryu

Sun-kyoung Seo

Baik-woo Lee

Myeong-soon Park

Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device

The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

Semiconductor devices

Semiconductor devices including guard ring and crack sensing circuit

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Semiconductor package

A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.

Semiconductor chip

A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.

Printed circuit board and semiconductor packages including the same

An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.

Integrated circuit package and integrated circuit module

A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An encapsulant may seal the semiconductor chip exposing the top surface of the second substrate. The conductive bumps of an upper unit package may be connected to the second substrate of the lower unit package.

Stack package implementing conductive support

A stack package may include a plurality of individual packages arranged in a stack. Each individual package may have a circuit substrate disposed on the upper and lower surfaces of a semiconductor chip. Through bonding wires, a lower circuit substrate may be electrically connected to the semiconductor chip, and an upper circuit substrate may be electrically connected to the lower circuit substrate. An upper package in the stack may be mechanically and electrically connected to the upper circuit substrate of a lower package in the stack through conductive bumps. The semiconductor chip may be surrounded by the upper and the lower circuit substrates, and molding resins. The individual packages may have the same conductive bump layout.

Growing community of inventors

Suwon-si, South Korea

Hyung-gil Baek