Samsung Electronics Co., Ltd.

Hyung-Dong Kim

Sang-Seok Kang

Jong-Hyun Choi

Chi-Sung Oh

Hyung-Shin Kwon

Choong-Sun Park

Yong-Hwan Jung

Seung-hoon Lee

Kwang-Hyun Kim

Gi-Gwan Park

Jung-Gun You

Dong-Il Seo

Jung-Sik Kim

Chan-jong Park

Hi-choon Lee

Sug-Hyun Sung

Ki-il Kim

Jae-Hoon Joo

Myung-Yoon Um

Gyu-hong Kim

Dong-il Seo

Jin-man Han

Sung-min Yim

Tae-Sik Son

Jang-Seok Choi

Byung-heon Kwak

Duk-ha Park

Yong-Hwan Cho

Byung-Hwan So

Woo-II Kim

Na-Rae Kim

Hee-Joong Oh

Young-Min Jang

A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

Semiconductor device and method for fabricating the same

A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Semiconductor devices and methods of manufacturing the same

Methods of manufacturing semiconductor devices

In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

Method of estimating self refresh period of semiconductor memory device

A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Semiconductor memory device

A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit

In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

Semiconductor device including wire bonding pads and pad layout method

The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Input buffer with wide input voltage range

The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Method and apparatus for controlling a high voltage generator in a wafer burn-in test

The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.

Semiconductor memory device for enhancing bitline precharge time

Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.

Pump circuits and methods for integrated circuits including first and second oscillators and first and second pumps

A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays. During a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second precharge voltage line, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.

Semiconductor memory device having mesh-type structure of precharge voltage line

The present invention discloses a semiconductor memory device and a voltage level control method thereof. The semiconductor memory device comprises multiple sub high voltage generators, multiple control circuits, a high voltage level detecting circuit, and a mode setting circuit. The multiple sub high voltage generators boost the high voltage level. The multiple control circuits control operations of each of the corresponding multiple sub high voltage generators responsive to each of corresponding high voltage detecting signals and to each of corresponding multiple control signals in the test mode. The high voltage level detecting circuit enabled by an active signal, detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting circuit sets the state of the multiple control signals responsive to the signals from the out side in the test mode. Performing the test by regulating the number of the multiple sub high voltage generators can prevent the semiconductor memory device from over kill. In addition, the test of the package state can be performed by enabling a few of the voltage generators than necessary for the full operation of the test mode.

Semiconductor memory device and voltage level control method thereof

A redundancy circuit is used to repair a normal column containing a defective normal memory cell. The redundancy circuit comprises a redundancy column containing redundancy memory cells and a plurality of programmable decoders. When any one of the plurality of programmable decoders enters a repair mode, a column pre-decoder for selecting a column containing a normal memory cell is disabled. Each of the programmable decoders can be configured to replace a column containing a defective normal memory cell in a single memory bank or a single memory bank group with a redundancy column. Since a defective column is replaced with a redundancy column in individual banks or bank groups, redundancy efficiency is greatly improved by allowing multiple normal columns containing defective cells to be replaced using a single redundancy column.

Growing community of inventors

Suwon-si, South Korea

Hyung-Dong Kim