Samsung Electronics Co., Ltd.

Hyung-Chan Choi

Chi-wook Kim

Byung-Hoon Jeong

Moo-Sung Chae

A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

Semiconductor memory device and method of arranging a decoupling capacitor thereof

Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Shared decoupling capacitance

There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDRmode, in a test operation mode.

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Suwon-si, South Korea

Hyung-Chan Choi