Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Hyung-Bok Choi

Dong-Woo Shin

Jong-Min Lee

Kwon Hong

Jin-Woong Kim

Chang-Rock Song

Dong-Sauk Kim

Il-Young Kwon

Hyeong-Soo Kim

Heung-Sik Kwak

Ho-Seok Lee

Chung-Tae Kim

Byung-Jun Park

A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: an inter-layer dielectric (ILD) layer formed on a semiconductor substrate; a contact plug formed in the ILD layer, such that a predetermined portion of the contact plug protrudes above the ILD layer; an etch stop layer formed on the ILD layer exposing a top portion of the contact plug; and a bottom electrode of a capacitor formed partially in the etch stop layer to be isolated from the ILD layer by the etch stop layer and the contact plug to prevent a direct contact with the ILD layer, and to be partially contacted with the contact plug.

Semiconductor device and method for fabricating the same

The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

Method for fabricating capacitor of semiconductor device

A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.

Capacitor and method for fabricating the same

A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact plugs, forming trenches exposing the storage node contact plugs, forming storage nodes in the trenches, forming a plasma barrier layer over the second insulation layer and the storage nodes, forming a capping layer over the plasma barrier layer and filled in the trenches, removing the capping layer, the plasma barrier layer, and the second insulation layer, forming a dielectric layer over the storage nodes, and forming a plate electrode over the dielectric layer.

Method for fabricating capacitor in semiconductor device

Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.

Semiconductor device and method of fabricating the same

The present invention relates to a method for fabricating a capacitor of a semiconductor memory device using an electrochemical deposition. The method in accordance with the present invention includes the steps of forming a contact hole in an insulating layer formed on a substrate; forming a plug in the contact hole, wherein the plug contains a nitride layer; forming a seed layer on the insulating layer and in the contact hole; forming a sacrificial layer including a trench overlapped with the contact hole; forming a Ru bottom electrode in the trench with electrochemical deposition; removing the sacrificial layer and exposing the Ru bottom electrode, wherein the seed layer not covered with the Ru bottom electrode is exposed; removing the exposed seed layer; forming a dielectric layer on the Ru bottom electrode; and forming a top electrode on the dielectric layer.

Method for fabricating capacitor using electrochemical deposition

The present invention provides a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug comprises a diffusion barrier layer and a seed layer for forming a lower electrode of a capacitor. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, whereby the leakage current may be reduced, and the capacitance of the capacitor may be increased.

Semiconductor memory device having a plug contacted to a capacitor electrode and method for fabricating the capacitor

Provided is a method for fabricating a capacitor using an electrochemical deposition method and Ce(NH ) (NO ) solution. The method includes the steps of: a) forming a contact hole in an insulation layer on a substrate; b) forming a plug including nitride in the contact hole; c) forming a Ru seed layer in the contact hole and on the insulation layer; d) forming a sacrificial layer including an open area overlapped with the contact hole on the Ru seed layer; e) forming a Ru layer for an electrode of the capacitor in the open area by performing electrochemical deposition; f) removing the sacrificial layer, whereby the Ru seed layer not covered with the Ru layer is exposed; and g) etching the exposed Ru seed layer by using an aqueous solution including Ce(NH ) (NO ) .

Method for fabricating capacitor using electrochemical deposition and wet etching

A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. Then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. The dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.

Method for forming a lower electrode by using an electroplating method

A method for fabricating a capacitor of a semiconductor device, comprising the steps of forming a seed layer over a semiconductor substrate, and forming multiple oxide layers on the seed layer, wherein wet etching of the multiple oxide layers decreases as the layers go up. A first opening is formed by exposing the seed layer by selectively dry etching the multiple oxide layer. A second opening is formed by wet etching the lateral surface of the first opening where the width of the first opening is expanded, wherein the lower part of the second opening is larger than the upper part. A bottom electrode is formed on the seed layer exposed at the bottom of the second opening, whereby the bottom electrode has an identical shape with the second opening, and the bottom electrode is formed with the ECD (Electro-Chemical Deposition) technique. The seed layer is exposed by removing the multiple oxide layer and then the exposed seed layer is removed. A dielectric layer is formed on the bottom electrode and a top electrode is formed on the dielectric layer.

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Ichon-shi, South Korea

Hyung-Bok Choi