Samsung Electronics Co., Ltd.

Hyunchul Hwang

Minsu Kim

Jongwoo Kim

Yonggeol Kim

Wonhyun Choi

Hyun Jae Lee

Jeongjin Lee

Hyun Shik Lee

Youngo Lee

Seungman Lim

Janghwan Yoon

A flip-flop (FF) includes a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line, a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line, a second NMOS transistor connecting a first node to the first NMOS transistor, a second PMOS transistor connecting the first node to the first PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, a keeper circuit connected to the first node to maintain a voltage level of the first node.

Flip-flop based on clock signal and pulse signal

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

Flip-flop, master-slave flip-flop, and operating method thereof

A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

Flip flop including serial stack structure transistors

A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.

Multi-bit flip-flop circuit with reduced area and reduced wire complexity

An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.

Circuit performing logical operation and flip-flop including the circuit

A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

Low power clock gating cell and an integrated circuit including the same

A low power flip-flop includes first to fourth signal generation circuits and an inverter. The first signal generation circuit receives the clock signal, the data input signal, and a first internal signal that is an output of the second signal generation circuit and generates a second internal signal. The inverter receives the first internal signal and generates an inverted first internal signal. The second signal generation circuit receives the first internal signal and the output signal that is an output of the third signal generation circuit, and generates the inverted output signal. The third signal generation circuit receives the clock signal and the inverted output signal and generates the output signal. The fourth signal generation circuit receives the inverted first internal signal, the second internal signal, and the clock signal and generates the first internal signal.

Low power flip-flop

High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

High speed flipflop circuit

A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

Clock gating circuit operates at high speed

In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Growing community of inventors

Suwon-si, South Korea

Hyunchul Hwang