Samsung Electronics Co., Ltd.

Hyun Woo Sim

Hyun Pil Kim

Seong Woo Ahn

Seong Hwan Ahn

Hun Kee Kim

Hyung Jong Kim

Yong Hwa Kim

Gi Hoon Lee

A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

Semiconductor device

A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

Sequence alignment method of vector processor

An electronic device is provided. The electronic device includes a display substrate and a connector connected to one side of the display substrate and having a dummy pattern. A cutting part is formed in the display substrate and the connector, and the cutting part is formed adjacent to the dummy pattern.

Electronic device and method for assembling the same

A digital signal processor is provided. The digital signal processor includes an execution circuit configured to receive a first data including first bits expressed in a signed magnitude method and a second data including second bits expressed in the signed magnitude method, and a control logic circuit configured to output a control signal that determines a type of operation on the first data and the second data based on a command signal, wherein the execution circuit is further configured to perform an operation on the first data and the second data according to a determined type of operation and generate a result of the operation.

Digital signal processor using signed magnitude and wireless communication receiver having the same

An electronic device and a method of manufacturing the electronic device is provided. The electronic device includes a housing, a structure that is formed on a surface of the housing and comprises a first pattern having a first at least one through-hole, a first speaker that is arranged in an interior of the housing to be adjacent to a first portion of the first pattern and is configured to output a sound, and a first microphone that is arranged in the interior of the housing to be adjacent to a second portion of the first pattern and is configured to receive a sound.

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Seoul, South Korea

Hyun Woo Sim