Samsung Electronics Co., Ltd.

Hyun-woo Park

Keun-cheol Hong

Byung-ho Min

Jung-ho Kim

Kyung-hoon Kim

Sun-hee Park

Ho-rang Jang

Kwang-ho Choi

Jin-ckuc Cho

Hyun-gi Baek

Jun-jin Gong

Yong-hyun Kil

Tak-hun Lee

Jun-Tin Gong

An air conditioner is provided. The air conditioner, which comprises a compressor, an outdoor heat exchanger, an indoor heat exchanger, a four-way valve, an accumulator, and an oil separator, and cools or heats a room by circulating a refrigerant. The air conditioner comprises a first block which is disposed on a first channel of the refrigerant between the oil separator and the four-way valve, and the first block is modular and includes a plurality of first control parts, and a second block which is disposed on a second channel of the refrigerant between the outdoor heat exchanger and the indoor heat exchanger, and the second block is modular and includes a plurality of second control parts.

Air conditioner

A protocol conversion and arbitration circuit may include: a protocol conversion circuit to receive signals complying with a second protocol used by a master, and to convert the received signals into signals complying with an intermediary protocol used by an internal bus of a slave; and a transform circuit to receive, from the protocol conversion circuit, and to convert the once-converted signals into signals complying with a first protocol used by the slave.

Protocol conversion and arbitration circuit, system having the same, and method for converting and arbitrating signals

In the analog-to-digital interfacing device, an input selector receives a plurality of analog signals and selectively outputs one of the analog signals based on a plurality of clock signals. An analog-to-digital converter converts the analog signals output from the selector to digital signals.

Analog-to-digital interfacing device and method of analog-to-digital interfacing

A digital signal processor capable of performing matrix operations, by which it is possible to use a method of matrix representation for the instruction level of the digital signal processor in order to effectively process a large amount of data, is provided. An apparatus included in the digital signal processor, for performing matrix operations, includes a data storage unit for storing operand data including matrix data in the form of a circular linked list and operation result data, an address generating unit for sequentially generating addresses required for performing matrix operations, the addresses including a series of addresses of first operand data, a series of addresses of second operand data, and a series of stored addresses of operation result data, whereby the addresses are sequentially generated according to the contents of the instruction words performed by the digital signal processor, and an operation unit for reading data positioned in the address generated by the data storage unit and performing operations according to the contents of the instruction words. It is possible to reduce the size of the program memory in the digital signal processor by providing a measure for effectively representing a digital signal processing algorithm. Accordingly, it is possible to reduce power consumption for reading the program memory, to thus allow electronic goods to be operated for a long time with small power consumption.

Matrix operation apparatus and digital signal processor capable of performing matrix operations

A convolutional encoder for a trellis coded modulation (TCM) system includes a first adder first outputting a first output bit by a modulo-two sum of a present input bit and a twice-delayed input bit of an upper stage, a present input bit and a once-delayed input bit of a lower stage, among 3-bit output bits; a second adder for outputting a second output bit by a modulo-two sum of a once-delayed input bit and a twice-delayed input bit of the upper stage and a present input bit of the lower stage; and a third adder for outputting a third output bit by a modulo-two sum of a present input bit of the upper stage and a once-delayed input bit of the lower stage. A trellis-coded modulation system includes a coder for receiving and encoding data; a mapper for inputting the remaining uncoded bit and the bit coded by the coder and converting them into a predetermined bit; a modulator for modulating the bit signal output from the mapper; and a controller for controlling the coder and mapper. Therefore, circuitry is simplified and the integration thereof is easy, while speed is improved.

Trellis-coded modulation system

A square computation circuit outputs data of 4-bits to 12-bits by inputting the input data of 2-bits to 6-bits, respectively. The relationships between inputs and outputs are obtained and then simplified, which simplifies circuit configuration and increases processing speed, over the case of the square computation performed using a conventional multiplier.

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Suwon-si, South Korea

Hyun-woo Park