Samsung Electronics Co., Ltd.

Fine M-tec Co., Ltd.

Hyun Taek Jung

Ji Eun Kim

Chan Kim

Suk-Soo Pyo

Tae Seong Kim

Sang-Hoon Jung

Jae Wook Joo

Ji Yean Kim

Chang Soo Kim

Gyu Hong Kim

Sung Chun Hong

Mark Pyo

A hinge device of a portable terminal with a foldable structure according to the present invention includes: housing positioned between one end of a first body and one end of a second body; first hinge blade and second hinge blade fixed to the first body and the second body, respectively, and supported against the housing to rotate at a predetermined angle between an 'unfolded position' in which the first body and the second body are placed on the same horizontal line and a ‘folded position’ in which the first body and the second body face each other and thus come into contact with each other; and first interlocking gear and second interlocking gear for interlocking the first hinge blade and the second hinge blade with each other so that the first hinge blade and the second hinge blade move relative to each other, wherein the first interlocking gear and the second interlocking gear are mounted on the corresponding housing in such a way as to rotate relative to each other by a predetermined angle around gear shafts by engaging with each other and, on the upper sides of the first interlocking gear and the second interlocking gear a plurality of first gear-side protrusions and second gear-side protrusions are arranged radially in circumferential directions around the gear shafts, and on the undersides of the first hinge blade and the second hinge blade a plurality of first blade-side protrusions and second blade-side protrusions engaging with the first gear-side protrusions and the second gear-side protrusions through rotations are arranged radially in circumferential directions around rotary axes of the first and second hinge blades.

Hinge device of portable terminal with foldable structure

Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Magnetic junction memory device and writing method thereof

A nonvolatile memory device includes a memory cell comprising a first variable resistor having one end connected to a first node, and the other end connected to a second node through a cell transistor; and a reference cell comprising a second variable resistor having one end connected to a third node, and the other end connected to a fourth node through a reference cell transistor, wherein gates of the cell transistor and the reference cell transistor are connected to a word line. Directions of a first read current flowing in the memory cell and a direction of a second read current flowing in the reference cell are opposite to each other.

Resistive memory device having read currents for a memory cell and a reference cell in opposite directions

A semiconductor device and a method of operating the same, the semiconductor device including a sense amplifier connected between a bit line and a complementary bit line; a first power supply circuit configured to select between supplying a power supply voltage to the first node and blocking the power supply voltage from the first node in response to a first control signal; a second power supply circuit configured to select between supplying a ground voltage to the second node and blocking the ground voltage from the second node in response to a second control signal; and a first boosting circuit configured to boost a voltage at the first node in response to a third control signal.

Semiconductor device and method of operating the same

A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.

Semiconductor memory devices including precharge using isolated voltages

In a semiconductor memory device having redundancy capability, a control signal generating circuit is included respectively for each of a predetermined number of redundant column select signal lines, to generate a predetermined number of block control signals by dividing a plurality of memory cell array blocks into a predetermined number of groups. A predetermined number of defective enable signal generating circuits are included for each of the redundant column select signal lines, to generate a predetermined number of redundant enable signals when defective addresses are input. The redundant column select signal lines are established for defective addresses based on the block control signals. A selection circuit is included respectively for each of the redundant column select signal lines to generate a select signal for selecting a redundant column select signal line corresponding to each of a predetermined number of redundant enable signals, in response to the block control signals. The efficiency of redundancy is thus improved by performing a redundancy operation by dividing a plurality of memory cell arrays into a predetermined number of groups for each of redundant column select signals.

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Seoul, South Korea

Hyun Taek Jung