Samsung Electronics Co., Ltd.

Hyun-Taek Jung

Suk-Soo Pyo

Tae-Joong Song

Artur Antonyan

Gyu-Hong Kim

Min-yeol Ha

Tae-Seong Kim

Sang-Seok Lee

Sang-seok Lee

Suk-soo Pyo

So-hee Hwang

A resistive memory device configured to calibrate a reference resistor includes a calibration resistor circuit including a calibration resistor, a first reference resistor, a first sense amplifier configured to compare input currents, a first switch set including a plurality of switches, and a controller configured to control the first switch set to allow the first sense amplifier to compare a first reference current passing through the first reference resistor with a first read current passing through a first memory cell during a read operation and compare the first reference current with a first calibration current passing through the calibration resistor during a calibrate operation. A path of the first reference current during the read operation is different from a path of the first reference current during the calibrate operation.

Resistive memory device providing reference calibration, and operating method thereof

A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

Device for supporting error correction code and test method thereof

Provided is a control signal generator for a sense amplifier, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.

Control signal generator for sense amplifier and memory device including the control signal generator

A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

Resistive memory device including a reference cell and method of controlling a reference cell to identify values stored in memory cells

A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

Resistive memory device having reduced chip size and operation method thereof

A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.

One-time programmable (OTP) memory device for reading multiple fuse bits

A one time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells provided at locations where a plurality of word lines and a plurality of bit lines cross each other, and a write circuit configured to sequentially program the OTP cells by selecting the bit lines one at a time and program a selected OTP cell connected to the selected bit line, wherein the write circuit is further configured to detect a voltage level of the selected bit line and select another bit line when the detected voltage level indicates that the selected OTP cell is in a programmed state.

One time programmable memory and a data writing method thereof

A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control signal based on a chip select signal and an external self refresh control signal. The memory cell array is refreshed in response to the internal auto refresh control signal. Because the semiconductor memory device internally generates the internal auto refresh control signal performing auto refresh operations, the semiconductor memory device may not be required to transmit to external devices for performing the auto refresh operations, and thus pins or pads for transmitting signals may be reduced and operation time may become faster.

Refresh control circuit and semiconductor memory device and memory system including the same

The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit circuit for storing refresh check bits corresponding to the memory blocks, respectively; a block select control circuit for setting refresh check bits of memory blocks to be refreshed to a checked state according to a first control of the memory controller; a using check bit circuit for storing using check bits corresponding to the memory blocks, respectively; a using check control circuit for setting refresh check bits of memory blocks to which access is requested to a checked state according to a second control of the memory controller; and a partial refresh control circuit for controlling the refresh operation such that memory blocks corresponding to checked using check bits or checked refresh check bits are refreshed according to a third control of the memory controller.

Memory device performing a partial refresh operation based on accessed and/or refreshed memory blocks and method thereof

A precharge circuit of a semiconductor memory device may include a precharge controller, a first precharge unit and a second precharge unit. The precharge controller may enable a first control signal in a precharge mode for a first operation, and may enable a second control signal in a precharge mode for a second operation. The first precharge unit may precharge a pair of I/O lines to a first voltage in response to the first control signal in the precharge mode for the first operation. The second precharge unit may precharge the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal in the precharge mode for the second operation.

Semiconductor memory devices including precharge circuit and methods for precharging

A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first time in response to an output signal and compares the input signal and the delayed input signal to generate a first signal. The first pulse generator generates a second signal in response to the input signal. The counter control circuit generates a count-up signal and a count-down signal in response to the first signal and the second signal. The counter generates the output signal in response to the count-up signal and the count-down signal to divide the first time by 2intervals, wherein n is a positive integer.

Circuit and method of controlling a delay of a semiconductor device

An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.

Memory device capable of refreshing data using buffer and refresh method thereof

The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.

System and method for controlling the access and refresh of a memory

A semiconductor memory device including a memory core, a data input circuit, a data output circuit, at least one data input/output line, at least one row control signal and at least one column control signal, wherein the data input circuit and the data output circuit are separately arranged, the memory core is positioned between the data input circuit and the data output circuit, the data input/output line extends from the data input circuit to the data output circuit across the memory core, and the row control signal line and the column control signal line simultaneously start from a first side of the data input circuit, proceed in along a side of the memory core to a corner of the memory core, the core being adjacent to the data output circuit, and then run from the corner to the opposite corner of the memory core.

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Seoul, South Korea

Hyun-Taek Jung