Samsung Electro-mechanics Co., Ltd.

Skhynix Inc.

Samsung Electronics Co., Ltd.

Samjin Pharmaceutical Co., Ltd.

Alantum Corporation

Incheon University Industry Academic Cooperation Foundation

Bamichem Co., Ltd.

Astech. Co., Ltd.

Hyun Tae Kim

Young Ghyu Ahn

Hwi Geun Im

Byoung Hwa Lee

Kyo Kwang Lee

Jin A Kim

Tae Sang Park

Young Jun Moon

Soon Min Hong

Sang Soo Park

Min Cheol Park

Doo Young Kim

Hee Jong Shin

Jae Woong Lee

Kyung Nam Hwang

Hyo Young Shin

Eui Hwan Cho

Ho Seok Kwon

Jin Ju Park

Se Hyun Kim

Jeong Ho Joo

Heung Kil Park

Jong Min Kim

Eu Joon Byun

Ho Jun Lee

Hye Mi Kang

Sung Pyo Hong

Beom Seock Oh

Soon Ju Lee

Sung Woo Lee

Eui-Hwan Cho

Soon Kil Ahn

Yong Won Seo

Min Hyo Ki

Kyu Ree Kim

Woo Heon Song

Byoung Woo Kim

Jong Bae Yoon

Ki Seok Park

Sung Ju Choi

Ho Tae Nam

Tai Won Choi

Ho Joon Park

So Yoon Jung

Keun Kuk Lee

Yong Bin Park

Sung Hyun Kang

Sung Hye Kim

Mi Jeong Chang

Woo Jin In

Kyoung Nam Hwang

Hyoung Min Cho

Woo Soon Whang

Woo-Heon Song

A data processing system is provided to include a storage unit and a controller in communication with the storage unit and configured to program write data to a first area as at least one of the plurality of storage areas with a priority over a second area as at least one of the plurality of storage areas and transfer data of the first area to the second area. The controller is further configured to adjust a size of the first area based on 1) a number of times saturated by the write data for the first area, a saturation occurring due to a size of the write data written to the first area being greater than a certain size and 2) an overflow size of the write data corresponding to a difference between the size of the write data and the certain size.

Data storage device and operating method thereof

A storage device may include: a storage comprising a plurality of memory blocks of memory cells for storing data; and a controller in communication with the storage to control operations of the storage and configured, in response to a write request from an external device to write data to the storage, to generate a first zone including one or more memory blocks and sequentially store the data from a first storage position of the first zone, and further configured, in response to a modification request from the external device to modify the data stored in the first zone, to identify a target memory block corresponding to the modification request and rewrite data to the target memory block.

Storage device and operating method thereof

The present technology includes a host configured to output a program request, a logical address, and data during a program operation, and a memory system configured to map a first physical address to the logical address, program the data to first memory blocks corresponding to the first physical address in a single level cell (SLC) method, program the data stored in the first memory blocks to a second memory block in a higher level cell method including a multi-level cell (MLC) method, a triple level cell (TLC) method, or a quadruple level cell (QLC) method after changing the first physical address to a second physical address, and transmit the second physical address to the host. The host outputs a read request and the second physical address to the memory system during a read operation of the data corresponding to the logical address.

Electronic system including host and memory system for performing read operation based on physical address received from the host

A data storage apparatus may include: a storage comprising a plurality of memory blocks; and a controller configured to: configure a write buffer pool by selecting a plurality of first memory blocks which are some of the plurality of memory blocks, manage remaining memory blocks except for the first memory blocks as second memory blocks, exclude one or more of the first memory blocks, whose data are migrated to the second memory blocks and add one or more of the second memory blocks to the write buffer pool.

Method and data storage apparatus for replacement of invalid data blocks due to data migration

The memory system includes: a first sub-buffer for storing an address map table; a second sub-buffer configured to sequentially store logical addresses, and store a latest received logical address in a specific region; a third sub-buffer including write buffers configured to store a size of data corresponding to each of the logical addresses; a storage device comprising memory blocks; a processor configured to control the storage device to store the data in memory blocks corresponding to the logical addresses using a SLC method; and an address manager configured to select at least two logical addresses comprising the latest received logical address. The processor is configured to control the storage device to store data read from memory blocks corresponding to the at least two logical addresses in a memory block using an MLC method. The address manager is configured to release a write buffer corresponding to the latest received logical address.

Memory system and operating method of the memory system

Disclosed are a novel rebamipide prodrug, a method for preparing the same, and use thereof. Also, a pharmaceutical composition comprising the novel rebamipide prodrug as an active ingredient is provided. The rebamipide prodrug is increased 25-fold in absorption rate compared to rebamipide itself, and can be applied to the prophylaxis or therapy of gastric ulcer, acute gastritis, chronic gastritis, xerophthalmia, cancer, osteoarthritis, rheumatoid arthritis, or obesity.

Rebamipide prodrugs, preparation method and use thereof

A memory system, a memory controller and a method for operating the memory system. The memory system manages a hot data pool and a cold data pool, each of which includes at least one among a plurality of memory blocks, writes read only data to the cold data pool, and controls the hot data pool and the cold data pool in garbage collection and wear leveling, thereby classifying data, less frequently updated, into cold data and improving the performance of garbage collection and wear leveling.

Memory system, memory controller and method for operating memory system

A multilayer electronic component includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode including an electrode layer disposed on the body and an Sn plating layer disposed on the electrode layer. A thickness of the body is defined as Tb, a thickness of the Sn plating layer is defined as Ts, Tb is 0.22 mm or less, and Ts is 4.5 &#x3bc;m or more.

Multilayered electronic component and board having the same mounted thereon

The present invention provides a novel pyridine derivative, a pharmaceutically acceptable salt thereof, a method for preparing the same, and a pharmaceutical composition containing the same as an active ingredient. The pyridine derivative according to the present invention inhibits Raf kinase (B-Raf, Raf-1, or B-RafV600E) and a vascular endothelial growth factor receptor (VEGFR2) involved in angiogenesis, and thus, can be favorably used for the prevention or treatment of melanoma, colorectal cancer, prostate cancer, thyroid cancer, lung cancer, pancreatic cancer, ovarian cancer, or the like, which is induced by RAS mutation.

Pyridine derivative inhibiting RAF kinase and vascular endothelial growth factor receptor, method for preparing same, pharmaceutical composition containing same, and use thereof

A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; first and second internal electrodes disposed in the ceramic body, the first internal electrode having first and second lead portions exposed to a first surface of the ceramic body in a width direction, and the second internal electrode having a third lead portion exposed to the first surface of the ceramic body in the width direction; first to third external electrodes disposed on the first surface of the ceramic body in the width direction to be connected to the first to third lead portions, respectively; and an insulation layer disposed on the first surface of the ceramic body in the width direction. Each of the first and second lead portions may be spaced apart from the third lead portion by a predetermined distance.

Multilayer ceramic capacitor and board having the same

A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b, (b&#x2212;b)/a satisfies 0.264&#x2266;(b&#x2212;b)/a&#x2266;0.638.

Multilayer ceramic capacitor having multilayer external electrodes and board having the same

A multilayer ceramic capacitor has a 3-terminal, vertical, multilayer structure in which portions of lead portions are not covered by external electrodes but are exposed to a mounting surface of a ceramic body. Insulating portions are disposed between the external electrodes on the mounting surface of the ceramic body. The insulating portions have an overlap portion covering portions of the external electrodes. 0.005&#x2266;i/e&#x2266;0.7 is satisfied, where i is a width of the overlap portion, and e is a width of the external electrode partially covered by the overlap portion.

There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 &#x3bc;m or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 &#x3bc;m or more.

A multilayer ceramic capacitor includes: a ceramic body including a plurality of dielectric layers and a plurality of first and second internal electrodes stacked in a width direction; a pair of first external electrodes disposed on a mounting surface of the ceramic body to be spaced apart from one another and connected to the plurality of first internal electrodes; a second external electrode disposed between the pair of first external electrodes on the mounting surface of the ceramic body and connected to the plurality of second internal electrodes; and a dummy electrode disposed on a surface of the ceramic body opposing the mounting surface of the ceramic body.

Multilayer ceramic capacitor and mounting board for mounting thereof

Growing community of inventors

Suwon-si, South Korea

Hyun Tae Kim