Skhynix Inc.

Samsung Electronics Co., Ltd.

Sk Hynic Inc.

Hyun-Sung Lee

Chun-Seok Jeong

Min-Su Kim

Jae-Phil Boo

Kwang-Hee Lee

Sang-Seon Lee

Jun-Gyu Ryu

Jong-Bok Kim

Kee-Teok Park

Woo-Sung We

Hyun-Joo Yun

A semiconductor device according to an embodiment includes a plurality of memory regions suitable for performing a refresh operation based on a row address signal; an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions; a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.

Semiconductor device and method of driving the same

A base chip including first to Nth delay units coupled in series, where N is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N&#x3e;X&#x2265;1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N&#x2265;Y&#x3e;X.

Base chip and semiconductor package including the same

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

Signal shifting circuit, base chip, and semiconductor system including the same

A bank control circuit includes an implicit signal generation unit suitable for activating an implicit signal when a first active signal corresponding to a bank which is in an activated state bank, among a plurality of banks; and a delay unit suitable for delaying the implicit signal by a predetermined time, wherein the bank corresponding to the first active signal is precharged based on the implicit signal and activated again based on the delayed implicit signal.

Bank control circuit and semiconductor memory device for data access with limited bandwidth for commands

Provided is a stacked memory device including a base die and a plurality of core dies. The base die may include: a weak cell address storage unit for storing weak cell addresses; a serialization unit for selecting at least one of the weak cell addresses as a target weak cell address, converting the selected target weak cell address into a serial weak cell address, and outputting a strobe signal synchronized with the serial weak cell address; a deserialization unit for storing the serial weak cell address based on the strobe signal, and converting the stored address into a parallel weak cell address based on a refresh end signal; and a refresh control unit for selecting the parallel weak cell address or a refresh address generated based on a refresh signal, and outputting a target address.

Stacked memory device having serial to parallel address conversion, refresh control unit, and pipe control unit

An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nsignals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.

Integrated circuit and precharge/active flag generation circuit

A semiconductor memory device comprising a memory cell array with a plurality of word lines, first and second dummy word lines, and a dummy word line driver suitable for separately driving the first and second dummy word lines for a wafer burn-in test where the word lines are driven by group.

Semiconductor memory device and method of wafer burn-in test for the same

The present invention discloses an apparatus for transporting wafers. The apparatus includes a tray having a sloped portion on which a wafer having a sidewall can be mounted, a plurality of guides that disposed about the tray, and a plurality of sensors for detecting the position of the sidewall of the wafer with respect to the tray on which it is mounted by sensing the position of the sidewall. The present invention also discloses an apparatus for polishing wafers having the apparatus for transporting wafers comprising the circular tray and a plurality of guides and a plurality of sensors above-mentioned.

Apparatus for transporting and polishing wafers

An apparatus for polishing a wafer includes a polishing station having a platen on which a polishing pad is installed, a polishing head having a membrane that contacts a surface of the wafer, the membrane securing the wafer and pressuring the wafer against the polishing pad, wherein the polishing station includes a transfer stage for loading the wafer on or unloading the wafer from the polishing head, and wherein the transfer stage includes a pedestal on which the wafer is placed and a fluid supply part for supplying a fluid into a boundary region between the wafer and the membrane to reduce a surface tension between the wafer and the membrane. Preferably, the apparatus further includes a stopper for preventing the wafer placed on the pedestal from being lifted up along with the membrane when the wafer is unloaded from the polishing head onto the pedestal.

Growing community of inventors

Gyeonggi-do, South Korea

Hyun-Sung Lee