Skhynix Inc.

Samsung Display Co., Ltd.

Samsung Sdi Co., Inc.

Hyun Sub Kim

Ie Ryung Park

Dong Sop Lee

Sung Yeob Cho

Jin Hong An

Ri A Ju

Dong Rak Kim

Jin-Woo Park

Ung-Soo Lee

Jae-Sun Lee

Jai-Hyuk Choi

Sung Bo Shim

Su-Hyuk Choi

Changwoo Shim

Cheho Lee

Jong Ki Lee

Jung Won Park

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Memory controller and operating method thereof

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

The present technology relates to an electronic device. More specifically, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device that outputs read data in response to a read enable signal provided from a memory controller includes a plurality of memory cells configured to store data, a plurality of page buffers configured to sense the data stored in the plurality of memory cells through a plurality of bit lines, and a data output controller configured to select a target page buffer to output data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller and control the selected target page buffer to output data stored in the selected target page buffer according to the read enable signal, while the read enable signal is input.

Memory device, storage device, and method of operating memory controller to output read data in response to read enable signal

A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.

Memory controller and method of operating the same

A memory system includes a memory device and a controller. The controller is coupled to the memory device through input/output (I/O) lines. The controller includes an interface component and a dummy power consumption component. The interface component performs a signal training operation for adjusting a timing of a clock signal, to which test data is synchronized. The dummy power consumption component performs a dummy power consumption operation while the signal training operation is performed.

Memory system

A memory system including: a memory device looping back a first clock to generate a second clock and outputting read data that are read from a memory cell region of the memory device in synchronization with the second clock; and a memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock. The read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme.

Apparatus and method for verifying reliability of data read from memory device through clock modulation, and memory system including the same

An organic light-emitting display apparatus includes: a substrate, and an organic light-emitting device disposed on the substrate. The organic light-emitting device includes a first electrode, a second electrode, and an intermediate layer including at least an organic emission layer. In addition, the organic light-emitting display apparatus further includes a thin film encapsulating layer disposed on the organic light-emitting device. The thin film encapsulating layer includes at least one inorganic film including a low temperature viscosity transition (LVT) inorganic material. The LVT inorganic material includes tin oxide and at least one of boron oxide (BO), bismuth oxide (BiO), barium oxide (BaO), and ammonium dihydrogen phosphate (NHHPO).

Organic light-emitting display apparatus and method for manufacturing the same

A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines extending generally in parallel in a second direction to intersect the first direction from the respective ends of the first lines and each second line having a width wider than the first line, and dummy patterns formed between the second lines.

Semiconductor device and method of manufacturing the same

An organic light-emitting display apparatus, includes a substrate including display area and a non-display area; a display device in the display area on the substrate; and a thin film encapsulating layer that covers the display device and includes an encapsulating inorganic layer and an encapsulating organic layer, the encapsulating inorganic layer including a plurality of inorganic layers and the encapsulating organic layer including a plurality of organic layers, at least one organic layer among the plurality of organic layers including a plurality of holes, and the plurality of holes being filled with an inorganic layer on the at least one organic layer.

Growing community of inventors

Yongin, South Korea

Hyun Sub Kim