Skhynix Inc.

Korea University Research and Business Foundation

Hyun Su Park

Chul Woo Kim

Choong Hwan Lee

Sang Geun Bae

Jin Cheol Sim

A signal driver circuit includes a pre-driving circuit, a driving signal generating circuit, a main driving circuit, and an output control circuit. The pre-driving circuit is configured to generate a first pre-driving signal and a second pre-driving signal based on an input signal and a clock signal. The driving signal generating circuit is configured to generate a pull-up driving signal and a pull-down driving signal based on the first pre-driving signal, the second pre-driving signal, and a complementary delayed output signal. The main driving circuit is configured to generate an output signal based on the pull-up driving signal and the pull-down driving signal. The complementary delayed output signal is generated by delaying the output signal. The output control circuit is configured to latch the output signal and configured to delay the output signal to generate a delayed output signal and the complementary delayed output signal.

Signal driver circuit, and a semiconductor apparatus using the same

A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.

Delay locked loop

Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.

An optical receiver includes a transimpedance amplifier that converts a current signal corresponding to an optical signal into a voltage signal. The transimpedance amplifier includes an input terminal receiving the current signal, an output terminal outputting the voltage signal, an inverting circuit including a pull-up device that pull-up drives the voltage signal of the output terminal according to the current signal, and a pull-down device that pull-down drives the voltage signal of the output terminal according to the current signal, a feedback resistor electrically connected between the input and output terminals, a first resistor electrically connected between the input terminal and the pull-up device, and a second resistor electrically connected between the input terminal and the pull-down device.

Optical receiver

An optical transceiver includes an optical transmitter and an optical receiver. The optical transmitter includes a laser diode configured to convert a current signal into an optical signal; a main driver comprising first and second output terminals that have a differential structure, the main driver configured to drive the first and second output terminals in response to differential input signals and to provide the current signal to the laser diode through the first output terminal; and an impedance balancer configured to match impedances of the first and second output terminals by adjusting the impedance of the second output terminal according to signal states of the first and second output terminals.

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Seoul, South Korea

Hyun Su Park